公开(公告)号：US09588880B2

公开(公告)日：2017-03-07

申请号：US13116751

申请日：2011-05-26

Applicant: Te-Lin Ping ,  Han-Chiang Su

Inventor： Te-Lin Ping ,  Han-Chiang Su

IPC: G06F12/02

CPC classification number: G06F12/02

Abstract: An adaptive memory address translation method includes the following steps. Multiple request instructions are received. A memory address corresponding to each request instruction includes a bank address. The memory addresses corresponding to the request instructions are translated, such that the bank addresses corresponding to at least one part of the any two adjacent request instructions are different. A numerical translation is utilized to translate the memory addresses corresponding to the request instructions, such that the memory addresses corresponding to the any two adjacent request instructions have less different bits.

Abstract translation: 自适应存储器地址转换方法包括以下步骤。 接收到多个请求指令。 对应于每个请求指令的存储器地址包括存储体地址。 与请求指令相对应的存储器地址被转换，使得对应于任何两个相邻请求指令的至少一部分的存储体地址不同。 使用数字转换来转换对应于请求指令的存储器地址，使得对应于任何两个相邻请求指令的存储器地址具有较少不同的位。

公开(公告)号：US20070028128A1

公开(公告)日：2007-02-01

申请号：US11192499

申请日：2005-07-29

Applicant: Te-Lin Ping

Inventor： Te-Lin Ping

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3265 ,  Y02D10/153 ,  Y02D50/20

Abstract: A power-saving method of continuous display and effective cost in a system that includes memory directly accessed by a CPU and at least one display device within vertical blanking. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the d display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process.

Abstract translation: 在包括由CPU直接访问的存储器和在垂直消隐中的至少一个显示设备的系统中的连续显示和有效成本的省电方法。 该方法包括以下步骤：发出省电相关消息; 省掉与节能相关的消息，其中没有设置省电相关标志; 设置省电相关标志; 设置CPU中的VID / FID待定位，其中发生d显示/显示的垂直消隐，并清除省电相关标志，其中设置了省电相关标志，并执行省电处理。

公开(公告)号：US20100299488A1

公开(公告)日：2010-11-25

申请号：US12534160

申请日：2009-08-03

Applicant: Te-Lin Ping ,  I-Huan Huang

Inventor： Te-Lin Ping ,  I-Huan Huang

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/10 ,  G06F13/1631

Abstract: A dynamic memory access method includes following steps. First, many data access commands are received. Each of the data access commands accesses a dynamic memory according to a page address and a bank address. Next, whether an access data to be accessed by the corresponding data access command is an instantaneous data or a non-instantaneous data is determined. Then, the page and bank addresses of each of the data access commands are respectively compared with a previously page and bank addresses at a previous time used for accessing the dynamic memory, such that an address hit status is obtained. Next, a service sequence is generated according to whether each of the data access commands is an instantaneous or instantaneous data and the address hit status of the commands. Finally, each of the data access commands is executed to access the dynamic memory sequentially according to the service sequence.

Abstract translation: 动态存储器访问方法包括以下步骤。 首先，接收到许多数据访问命令。 每个数据访问命令根据页面地址和银行地址访问动态存储器。 接下来，确定由相应的数据访问命令访问的访问数据是否是瞬时数据或非瞬时数据。 然后，将每个数据访问命令的页面和存储体地址分别与用于访问动态存储器的先前时间的页面和存储体地址进行比较，从而获得地址命中状态。 接下来，根据每个数据访问命令是瞬时数据还是瞬时数据以及命令的地址命中状态来生成服务序列。 最后，执行每个数据访问命令以根据服务顺序顺序地访问动态存储器。

公开(公告)号：US20100180141A1

公开(公告)日：2010-07-15

申请号：US12426926

申请日：2009-04-20

Applicant: Te-Lin Ping ,  Yao-Cheng Chuang

Inventor： Te-Lin Ping ,  Yao-Cheng Chuang

IPC: G06F1/12

CPC classification number: G06F1/10

Abstract: A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index.

Abstract translation: 电路系统定期检查系统环境监视值，然后在环境调整查找表中获取与系统环境监视值对应的系统环境监视值索引。 最后，电路系统根据对应于系统环境监控值的延迟调整值调整信号延迟时间。

公开(公告)号：US07421600B2

公开(公告)日：2008-09-02

申请号：US11192499

申请日：2005-07-29

Applicant: Te-Lin Ping

Inventor： Te-Lin Ping

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3265 ,  Y02D10/153 ,  Y02D50/20

Abstract: A power-saving method of continuous display and effective cost in a system that includes memory directly accessed by a CPU and at least one display device within vertical blanking. The method includes the following steps: issuing a Power-saving related message; dropping the Power-saving related message, wherein a Power-saving related flag is not set; setting the Power-saving related flag; setting a VID/FID pending bit in the CPU, wherein the vertical blanking of the display/displays occurs and clearing the Power-saving related flag, wherein the Power-saving related flag is set, and executing a power saving process.

Abstract translation: 在包括由CPU直接访问的存储器和在垂直消隐中的至少一个显示设备的系统中的连续显示和有效成本的节电方法。 该方法包括以下步骤：发出省电相关消息; 省掉与节能相关的消息，其中没有设置省电相关标志; 设置省电相关标志; 设置CPU中的VID / FID待处理位，其中发生显示/显示的垂直消隐，并清除省电相关标志，其中设置了省电相关标志，并执行省电处理。

公开(公告)号：US10908975B2

公开(公告)日：2021-02-02

申请号：US13064448

申请日：2011-03-25

Applicant: Te-Lin Ping ,  Shi-Yen Huang

Inventor： Te-Lin Ping ,  Shi-Yen Huang

IPC: G06F9/54 ,  H04N19/44 ,  H04N19/42 ,  H04N19/423

Abstract: A computer system architecture including a first buffer, a second buffer, a sub-system and a CPU is provided. The sub-system carries out a first task to obtain first returned information, stores the first returned information in the first buffer and sets up a first occupancy flag to the first buffer. Next, the sub-system carries out a second task to obtain second returned information, stores the second returned information in the second buffer, and sets up a second occupancy flag to the second buffer. The CPU reads the first returned information and eliminates the first occupancy flag. After the second returned information is stored in the second buffer and the first occupancy flag is eliminated, the sub-system continuously carries out a third task to obtain third returned information, stores the third returned information in the first buffer, and sets up the first occupancy flag to the first buffer.

公开(公告)号：US08499126B2

公开(公告)日：2013-07-30

申请号：US13042013

申请日：2011-03-07

Applicant: Te-Lin Ping ,  I-Huan Huang

Inventor： Te-Lin Ping ,  I-Huan Huang

IPC: G06F12/00

CPC classification number: G06F12/00

Abstract: A memory control system includes a first queue unit, a second queue unit, a first transforming unit, a second transforming unit, an arbiter and a control unit. The first queue unit temporarily stores multiple first request instructions. The second queue unit temporarily stores multiple second request instructions. The first transforming unit selectively re-assigns memory addresses corresponding to these first request instructions. The second transforming unit selectively re-assigns memory addresses corresponding to these second request instructions. The arbiter performs immediate scheduling of the first request instructions and the second request instructions to the memory. The control unit compares bandwidths of the first request instructions with bandwidths of the second request instructions, and controls the first transforming unit and the second transforming unit to perform re-assigning operations or not according to compared results.

Abstract translation: 存储器控制系统包括第一队列单元，第二队列单元，第一变换单元，第二变换单元，仲裁器和控制单元。 第一队列单元临时存储多个第一请求指令。 第二队列单元临时存储多个第二请求指令。 第一变换单元选择性地重新分配对应于这些第一请求指令的存储器地址。 第二变换单元选择性地重新分配对应于这些第二请求指令的存储器地址。 仲裁器将第一请求指令和第二请求指令立即调度到存储器。 控制单元将第一请求指令的带宽与第二请求指令的带宽进行比较，并且根据比较结果控制第一变换单元和第二变换单元进行重新分配操作。

公开(公告)号：US08171329B2

公开(公告)日：2012-05-01

申请号：US12426926

申请日：2009-04-20

Applicant: Te-Lin Ping ,  Yao-Cheng Chuang

Inventor： Te-Lin Ping ,  Yao-Cheng Chuang

IPC: G06F1/12

CPC classification number: G06F1/10

Abstract: A circuit system periodically checks a system-environment monitor value, and then obtains a system-environment monitor value index corresponding to the system-environment monitor value in the environment-adjustment look-up table. Finally, the circuit system adjusts a signal delay time according to a delay adjustment value corresponding to the system-environment monitor value index.

Abstract translation: 电路系统定期检查系统环境监视值，然后在环境调整查找表中获取与系统环境监视值对应的系统环境监视值索引。 最后，电路系统根据对应于系统环境监控值的延迟调整值调整信号延迟时间。

公开(公告)号：US20110235722A1

公开(公告)日：2011-09-29

申请号：US13064448

申请日：2011-03-25

Applicant: Te-Lin Ping ,  Shi-Yen Huang

Inventor： Te-Lin Ping ,  Shi-Yen Huang

IPC: H04N7/26 ,  G06F9/46

CPC classification number: G06F9/544 ,  H04N19/42 ,  H04N19/423 ,  H04N19/44

Abstract: A computer system architecture including a first buffer, a second buffer, a sub-system and a CPU is provided. The sub-system carries out a first task to obtain first returned information, stores the first returned information in the first buffer and sets up a first occupancy flag to the first buffer. Next, the sub-system carries out a second task to obtain second returned information, stores the second returned information in the second buffer, and sets up a second occupancy flag to the second buffer. The CPU reads the first returned information and eliminates the first occupancy flag. After the second returned information is stored in the second buffer and the first occupancy flag is eliminated, the sub-system continuously carries out a third task to obtain third returned information, stores the third returned information in the first buffer, and sets up the first occupancy flag to the first buffer.

Abstract translation: 提供了包括第一缓冲器，第二缓冲器，子系统和CPU的计算机系统架构。 子系统执行第一任务以获得第一返回信息，将第一返回信息存储在第一缓冲器中，并将第一占用标志设置到第一缓冲器。 接下来，子系统执行第二任务以获得第二返回信息，将第二返回信息存储在第二缓冲器中，并将第二占用标志设置到第二缓冲器。 CPU读取第一个返回的信息，并消除第一个占用标志。 在将第二返回信息存储在第二缓冲器中并且消除第一占用标志之后，子系统连续地执行第三任务以获得第三返回信息，将第三返回信息存储在第一缓冲器中，并且设置第一 占用标志到第一个缓冲区。

公开(公告)号：US20070067502A1

公开(公告)日：2007-03-22

申请号：US11233590

申请日：2005-09-22

Applicant: Te-Lin Ping

Inventor： Te-Lin Ping

IPC: G06F3/00

CPC classification number: G06F9/4881

Abstract: A method for preventing the long latency event in the working procedure of the processor is disclosed, wherein the method comprises one step of checking whether a status happens or not. When the status happens, the processor would release the resource for specific time duration to process other works in order to prevent the long latency event.

Abstract translation: 公开了一种用于防止处理器的工作过程中长时间延迟事件的方法，其中该方法包括检查状态是否发生的一个步骤。 当状态发生时，处理器将释放特定持续时间的资源以处理其他工作，以防止长延迟事件。