摘要:
A signal processor for use with an imaging sensor system that provides enhanced video imagery. The signal processor may be coupled to a FLIR system, for example, which comprises a plurality of detectors that are scanned across an image scene and reference temperature source during separate portions of each scan cycle. The signal processor comprises an input processor coupled to the imaging sensor system which processes analog signals derived from each of the plurality of detectors. The input processor normalizes the analog signals relative to one another during the active portion of the scan cycle based upon stored data derived from a predetermined sensor responsivity calibration procedure. This normalization function equalizes the gains associated with all channels of the sensor system. The input processor also restores the DC levels of each of the sensor channels to respective DC values related to the reference temperature source during the inactive portion of the scan cycle. This function is performed during the calibration procedure and while the system is in operation. The input processor digitizes the signals which are applied to a scan converter. The scan converter stores the digitized signals and converts the stored signals into signals which are compatible with a video monitor employed to view the image. An output processor is coupled to the scan converter that is employed to process signals in a manner which permits software-controlled digitized image enhancement thereof, and which converts the enhanced signals into analog video output signals compatible with the video monitor.
摘要:
A stroke-mode CRT display having a Z channel (video) compensation circuit is disclosed. The function of the compensation circuit to correct for the lag of the X and Y channels in relation to the Z channel. The compensation circuit is designed so that transfer function characteristic is identical to that of the respective deflection amplifier and coil circuitry for the X and Y channels. With the compensation circuitry, the X, Y and Z channel signals are in proper relation to one another, and high quality symbology is achieved.
摘要:
A symbol/raster generator system for a CRT display system is described, having the capability of generating raster-scanned display signals or vector symbology. The system includes a polar coordinate transformation circuit which transforms polar coordinate beam deflection data into corresponding X and Y beam deflection control signals. The system includes an angle accumulator for accumulating incremental angular data over time, and sine and cosine PROMS for providing the sine and cosine of the accumulated angle value. X and Y multiplier circuits provide respective incremental dX and dY values corresponding to the respective products of the cosine and sine values with a step size value dR. The incremental dX and dY values are accumulated over time to provide the X and Y beam deflection signals. The system further includes circuits for providing the angle data and step size dR so as to generate rasters, 8 and 16-side characters, curved and slanted characters, conic symbology, and other types of special symbols. The rasters can be arc-scanned rasters as required in radar displays, e.g., plan position indicator (PPI), SAR, angular and radial scan. The system provides an integrated and highly versatile raster/symbol generator for CRT displays.
摘要:
Disclosed herein is a linear deflection amplifier which is suitable for processing horizontal sweep signals for driving a magnetic deflection yoke of a radar CRT PPI (Plan Position Indicator) display. The amplifier features a transadmittance feedback where output current follows input voltage. Flyback resonance is derived by a shunt capacitor coupled to an FET switch. Low cross-over distortion and temperature compensation of components within the system is achieved by use of a modified class B power MOSFET push-pull configuration.
摘要:
A system is disclosed for generating a circle on a television raster display utilizing digital techniques. An x coordinate counter, a y coordinate counter, a radius number, and a radius +.delta. number, in parallel to each other, are connected to the input terminals of a multiplex switch. The multiplex switch selectively provides an output signal of the above number generators to a programmable read only memory (PROM). The memory in turn sequentially provides an output signal representing the square of the input number, i.e., x.sup.2, y.sup.2, r.sup.2 and (r + .delta.).sup.2. The numbers x.sup.2 and y.sup.2 are added by an adder and the number x.sup.2 + y.sup.2 is compared by a first comparator, with the number r.sup.2 and an output is provided if x.sup.2 + y.sup.2 .gtoreq. r.sup.2. The numbers x.sup.2 + y.sup.2 is also compared by a second comparator, with the number (r+.delta.).sup. 2 and an output signal is provided if x.sup.2 + y.sup.2