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    SYSTEMS AND METHODS FOR TRAINING AND VALIDATION OF MACHINE-LEARNING-BASED RF TRANSMIT/RECEIVE SYSTEMS
    1.
    发明公开
    SYSTEMS AND METHODS FOR TRAINING AND VALIDATION OF MACHINE-LEARNING-BASED RF TRANSMIT/RECEIVE SYSTEMS 审中-公开

    公开(公告)号：US20240364432A1

    公开(公告)日：2024-10-31

    申请号：US18643943

    申请日：2024-04-23

    Applicant: Tektronix, Inc.

    Inventor： Christopher N. White ,  Alexander Krauska ,  Alejandro C. Buritica

    IPC: H04B17/00 ,  H04B17/10 ,  H04B17/15

    CPC classification number: H04B17/0085 ,  H04B17/101 ,  H04B17/191

    Abstract: A test and measurement device includes a signal generator to generate a test signal, a signal analyzer to receive a response signal from an adaptive system under test (SUT), communications ports to allow reception of the response signal, and one or more processors to send a signal to the signal generator to generate a first test signal, receive a response signal from the signal analyzer, measure performance of the response signal, and report the performance to at least one of the SUT and a user workspace on the test and measurement device. A method of testing a system under test (SUT) includes generating and sending a test signal with a signal generator, receiving a response signal from the SUT at a signal analyzer, measuring performance of the response signal with respect to the test signal, and reporting the performance to at least one of the SUT and a user workspace.

    USE OF A DATA SYMBOL ERROR BOUNDARY VIOLATION AS A TRIGGER SOURCE FOR SIGNAL CAPTURE AND STORAGE
    2.
    发明申请
    USE OF A DATA SYMBOL ERROR BOUNDARY VIOLATION AS A TRIGGER SOURCE FOR SIGNAL CAPTURE AND STORAGE 有权

    公开(公告)号：US20250044352A1

    公开(公告)日：2025-02-06

    申请号：US18779763

    申请日：2024-07-22

    Applicant: Tektronix, Inc.

    Inventor： Christopher N. White

    IPC: G01R31/317 ,  G01R31/302

    Abstract: A test and measurement instrument includes an antenna to receive signals containing symbols from a system under test (SUT), one or more analog-to-digital converters (ADC) to sample the signals received from the SUT, a memory to selectively store samples from the ADC, and one or more processors configured to execute code that causes the one or more processors to: receive samples from the ADC, analyze the samples from the ADC to determine whether one or more of the symbols received from the SUT has exceeded an expected modulation boundary for the one or more symbols; identifying a time at which the one or more symbols exceeded the expected modulation boundary as a trigger time; and store samples from a predetermined window of time surrounding the trigger time in the memory.

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