SYSTEMS AND METHODS FOR TRAINING AND VALIDATION OF MACHINE-LEARNING-BASED RF TRANSMIT/RECEIVE SYSTEMS

    公开(公告)号:US20240364432A1

    公开(公告)日:2024-10-31

    申请号:US18643943

    申请日:2024-04-23

    CPC classification number: H04B17/0085 H04B17/101 H04B17/191

    Abstract: A test and measurement device includes a signal generator to generate a test signal, a signal analyzer to receive a response signal from an adaptive system under test (SUT), communications ports to allow reception of the response signal, and one or more processors to send a signal to the signal generator to generate a first test signal, receive a response signal from the signal analyzer, measure performance of the response signal, and report the performance to at least one of the SUT and a user workspace on the test and measurement device. A method of testing a system under test (SUT) includes generating and sending a test signal with a signal generator, receiving a response signal from the SUT at a signal analyzer, measuring performance of the response signal with respect to the test signal, and reporting the performance to at least one of the SUT and a user workspace.

    FLEXIBLE ARBITRARY WAVEFORM GENERATOR AND INTERNAL SIGNAL MONITOR

    公开(公告)号:US20240027507A1

    公开(公告)日:2024-01-25

    申请号:US18354584

    申请日:2023-07-18

    CPC classification number: G01R31/00 G01R13/00

    Abstract: A test and measurement instrument has an arbitrary waveform generator having at least two waveform generators. Each waveform generator includes a signal generator to generate in-phase (I) and quadrature (Q) digital signals according to a selected signal type for a digital constituent output signal, a pulse envelope sequencer to modulate amplitude of the I and Q digital signals, and one or more multipliers to combine the I and Q digital signals with a carrier signal to produce the digital constituent output signal. The arbitrary waveform generator includes a stream manager to produce modulation descriptor words for the waveform generators, a summing block to selectively combine digital constituent output signals to produce a digital multi-constituent output signal, a digital-to-analog converter to convert the digital multi-constituent output signal to an analog output signal, and an internal signal analyzer to receive an analyzer input of one of more of the digital output signals.

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