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公开(公告)号：US20120166902A1
公开(公告)日：2012-06-28
申请号：US12929031
申请日：2010-12-22
IPC分类号： G06F11/26
CPC分类号： G06F11/267
摘要： An integrated circuit 2 provided with multiple functional units 6, 8, 10, 12, 14, and 16 for performing data processing operations as part of advancing execution of a data processing task by the integrated circuit 2. Activity detection circuitry 26 determines which of these functional circuits is inactive at the given time. If a functional is inactive, then scan control circuitry 28 may perform a scan test operation thereon using an associated serial scan chain 34, 36, 38, 40, 42, 44.
摘要翻译： 具有多个功能单元6,8,10,12,14和16的集成电路2，用于执行数据处理操作，作为由集成电路2提前执行数据处理任务的一部分。活动检测电路26确定这些 功能电路在给定的时间无效。 如果功能不活动，则扫描控制电路28可以使用相关联的串行扫描链34,36,38,40,42,44在其上执行扫描测试操作。
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公开(公告)号：US08468405B2
公开(公告)日：2013-06-18
申请号：US12929031
申请日：2010-12-22
IPC分类号： G01R31/28
CPC分类号： G06F11/267
摘要： An integrated circuit 2 provided with multiple functional units 6, 8, 10, 12, 14, and 16 for performing data processing operations as part of advancing execution of a data processing task by the integrated circuit 2. Activity detection circuitry 26 determines which of these functional circuits is inactive at the given time. If a functional is inactive, then scan control circuitry 28 may perform a scan test operation thereon using an associated serial scan chain 34, 36, 38, 40, 42, 44.
摘要翻译： 具有多个功能单元6,8,10,12,14和16的集成电路2，用于执行数据处理操作，作为由集成电路2提前执行数据处理任务的一部分。活动检测电路26确定这些 功能电路在给定的时间无效。 如果功能不活动，则扫描控制电路28可以使用相关联的串行扫描链34,36,38,40,42,44在其上执行扫描测试操作。
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公开(公告)号：US07913131B2
公开(公告)日：2011-03-22
申请号：US12007144
申请日：2008-01-07
IPC分类号： G01R31/28
CPC分类号： G01R31/31858
摘要： A scan chain cell 24 is provided with a built-in delay testing capability. An inverter 32 generates an inverted form of the cell output which is available within the scan chain cell 24 for rapid use in forming a transition at the cell output Q. Clock gating circuitry 36, 38 is responsive to a hold signal to block the functional path 34, 26, 28 through the scan chain cell and hold the output signal when desired. The functional clock clk may be clocked twice at speed to trigger capture of the results of processing the output of the scan chain cell 24 for the non-inverted value followed by the (internally generated) inverted value, i.e. a signal transition. In this way delay testing of the functional circuitry 18 can be performed.
摘要翻译： 扫描链单元24具有内置的延迟测试能力。 反相器32产生单元输出的反向形式，其在扫描链单元24内可用，用于在单元输出Q形成转换时快速使用。时钟选通电路36,38响应于保持信号以阻塞功能路径 34,26,28，并且在需要时保持输出信号。 功能时钟clk可以以两倍的速度进行计时，以触发捕获扫描链单元24的输出的结果，用于非反转值，后跟（内部产生的）反相值即信号转换。 以这种方式，可以执行功能电路18的延迟测试。
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公开(公告)号：US07308631B2
公开(公告)日：2007-12-11
申请号：US10242439
申请日：2002-09-13
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318558
摘要： A wrapper serial scan chain used during test of an integrated circuit is provided for a first functional block of circuitry and is segmented to provide a separately accessible wrapper serial scan chain segment that can be used to apply test to a second functional block of circuitry while bypassing the rest of the main wrapper serial scan chain.
摘要翻译： 为集成电路测试期间使用的封装序列扫描链被提供用于电路的第一功能块，并且被分段以提供可单独访问的包装串行扫描链段，其可以用于在绕过旁路时将测试应用于电路的第二功能块 主要包装系列扫描链的其余部分。
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公开(公告)号：US06999900B2
公开(公告)日：2006-02-14
申请号：US10812309
申请日：2004-03-30
IPC分类号： G06F19/00
CPC分类号： G06F11/267 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C2029/3202
摘要： In order to test the memory access signal connections between a data processing circuit, such as a processor core 2, and a memory 4, a subset of memory access signal connections 8 are provided with associated scan chain cells 10 so that they may be directly tested. The remainder memory access signal connections 12 which are common to all the expected configurations of the memory 4 are tested by being driven by the processor core 2 itself with data being passed through the memory and captured back within the processor core 2 for checking.
摘要翻译： 为了测试数据处理电路（例如处理器核心2）和存储器4之间的存储器访问信号连接，存储器访问信号连接8的子集被提供有相关联的扫描链单元10，使得它们可以被直接测试 。 存储器4的所有预期配置共同的剩余存储器访问信号连接12被处理器核心2本身驱动，数据被传送通过存储器并被捕获回到处理器核心2中进行检查。
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公开(公告)号：US20090177935A1
公开(公告)日：2009-07-09
申请号：US12007144
申请日：2008-01-07
IPC分类号： G01R31/3183
CPC分类号： G01R31/31858
摘要： A scan chain cell 24 is provided with a built-in delay testing capability. An inverter 32 generates an inverted form of the cell output which is available within the scan chain cell 24 for rapid use in forming a transition at the cell output Q. Clock gating circuitry 36, 38 is responsive to a hold signal to block the functional path 34, 26, 28 through the scan chain cell and hold the output signal when desired. The functional clock clk may be clocked twice at speed to trigger capture of the results of processing the output of the scan chain cell 24 for the non-inverted value followed by the (internally generated) inverted value, i.e. a signal transition. In this way delay testing of the functional circuitry 18 can be performed.
摘要翻译： 扫描链单元24具有内置的延迟测试能力。 反相器32产生单元输出的反向形式，其在扫描链单元24内可用，用于在单元输出Q形成转换时快速使用。时钟选通电路36,38响应于保持信号以阻塞功能路径 34,26,28，并且在需要时保持输出信号。 功能时钟clk可以以两倍的速度进行计时，以触发捕获扫描链单元24的输出的结果，用于非反转值，后跟（内部产生的）反相值即信号转换。 以这种方式，可以执行功能电路18的延迟测试。
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公开(公告)号：US07085978B2
公开(公告)日：2006-08-01
申请号：US10244561
申请日：2002-09-17
IPC分类号： G01R31/28
CPC分类号： G01R31/04
摘要： Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain. These wrapper cells can then be used to validate that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, e.g., a system-on-chip design.
摘要翻译： 测试信号与集成电路中的电路功能块的连接是使用包装器串行扫描链的封装序列扫描链单元进行的。 然后可以使用这些封装单元来验证正确的信号正在达到测试信号输入，并且当电路的功能块被并入更大的设计中时，正确的信号从测试信号输出到达它们的目的地， 芯片设计。
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8.发明授权Resetting latch circuits within a functional circuit and a test wrapper circuit 有权复位功能电路和测试包装电路内的锁存电路公开(公告)号：US07080299B2
公开(公告)日：2006-07-18
申请号：US10356587
申请日：2003-02-03
IPC分类号： G01R31/28
CPC分类号： G01R31/318555 , G01R31/318508
摘要： Within an integrated circuit 2 a functional block of circuitry 6 has an associated test wrapper circuit 10. The functional block of circuitry 6 includes functional latches 14 at least some of which may also serve as shared test latches 18 within the test wrapper circuitry 10. Separate reset signals reset_wrp, reset_int are generated for the test latches and shared test latches 18 as distinct from the functional latches 14. Thus, during testing, power consuming activity of the functional latches 14 can be suppressed if it is not desired to test the functional block of circuitry 6 itself. This is a particularly useful technique when a functional block of circuitry 6 is required to operate in an extest mode in which output signals from it are required to be driven so that other elements in the overall design may be tested and yet the internal action of the functional block of circuity 6 is not under test.
摘要翻译： 在集成电路2内，电路6的功能块具有相关联的测试包装电路10。 电路6的功能块包括功能锁存器14，其中的至少一些还可以用作测试包装电路10内的共享测试锁存器18。 对于与功能锁存器14不同的测试锁存器和共享测试锁存器18产生分离的复位信号reset_wrp，reset_int。 因此，在测试期间，如果不希望测试电路6本身的功能块，则可以抑制功能锁存器14的功耗活动。 这是一个特别有用的技术，当需要电路6的功能块以最外部模式工作时，其中需要驱动来自其的输出信号，使得整体设计中的其他元件可以被测试，然而内部动作 功能块电路6未经测试。
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