公开(公告)号：US20120166902A1

公开(公告)日：2012-06-28

申请号：US12929031

申请日：2010-12-22

申请人： Teresa Louise McLaurin ,  Gerard Richard Williams

发明人： Teresa Louise McLaurin ,  Gerard Richard Williams

IPC分类号： G06F11/26

CPC分类号： G06F11/267

摘要： An integrated circuit 2 provided with multiple functional units 6, 8, 10, 12, 14, and 16 for performing data processing operations as part of advancing execution of a data processing task by the integrated circuit 2. Activity detection circuitry 26 determines which of these functional circuits is inactive at the given time. If a functional is inactive, then scan control circuitry 28 may perform a scan test operation thereon using an associated serial scan chain 34, 36, 38, 40, 42, 44.

摘要翻译： 具有多个功能单元6,8,10,12,14和16的集成电路2，用于执行数据处理操作，作为由集成电路2提前执行数据处理任务的一部分。活动检测电路26确定这些 功能电路在给定的时间无效。 如果功能不活动，则扫描控制电路28可以使用相关联的串行扫描链34,36,38,40,42,44在其上执行扫描测试操作。

公开(公告)号：US07269766B2

公开(公告)日：2007-09-11

申请号：US10025816

申请日：2001-12-26

申请人： Richard Slobodnik ,  Stephen John Hill ,  Gerard Richard Williams

发明人： Richard Slobodnik ,  Stephen John Hill ,  Gerard Richard Williams

IPC分类号： G11C29/00

CPC分类号： G11C29/16

摘要： A self-test controller 10 is responsive to scanned in self-test instructions to carry out test operations including generating a sequence of memory addresses that is specified by the self-test instruction. Combining multiple such self-test instructions allows a custom test methodology to be built up by a user using a generic self-test controller 10.

摘要翻译： 自测试控制器10响应于在自检指令中扫描以执行测试操作，包括生成由自检指令指定的存储器地址序列。 组合多个这样的自检指令允许由用户使用通用自检控制器10构建自定义测试方法。

公开(公告)号：US07240144B2

公开(公告)日：2007-07-03

申请号：US10815961

申请日：2004-04-02

申请人： Tan Ba Tran ,  Gerard Richard Williams ,  David Terrence Matheny ,  David Walter Flynn

发明人： Tan Ba Tran ,  Gerard Richard Williams ,  David Terrence Matheny ,  David Walter Flynn

IPC分类号： G06F12/00

CPC分类号： G06F13/1657 ,  G06F13/28

摘要： A data processor core 10 comprising: a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory 120 associated with said data processor core; a data processing portion 12 operable to perform data processing operations; a read/write port 40 operable to transfer data from said processor core to at least two buses 75A, 75B said at least two buses being operable to provide data communication between said processor core 10 and said at least one memory 120, said at least one memory 120 comprising at least two portions 120A, 120B, each of said at least two buses 75A, 75B being operable to provide data access to respective ones of said at least two portions 120A, 120B; arbitration logic 110 associated with said read/write port 40; wherein said arbitration logic is operable to route a data access request requesting access of data in one portion of said at least one memory received from said memory access interface to one of said at least two buses providing access to said one portion of said at least one memory and to route a further data access request requesting access of data in a further portion of said at least one memory received from said data processing portion to a further one of said at least two buses providing access to said further portion of said at least one memory, said routing of said data access requests being performed during the same clock cycle.

摘要翻译： 一种数据处理器核心10，包括：存储器访问接口部分30，可操作以在外部数据源与与所述数据处理器核心相关联的至少一个存储器120之间执行数据传输操作; 数据处理部分12，用于执行数据处理操作; 读/写端口40，其可操作以将数据从所述处理器核传输到至少两个总线75A，75B，所述至少两个总线可操作以在所述处理器核心10和所述至少一个存储器120之间提供数据通信， 至少一个存储器120包括至少两个部分120A，120B，所述至少两个总线75A，75B中的每一个可操作以提供对所述至少两个部分120A，120B中的相应部分的数据访问; 与所述读/写端口40相关联的仲裁逻辑110; 其中所述仲裁逻辑可操作用于将请求数据访问的数据访问请求路由到从所述存储器访问接口接收的所述至少一个存储器的一部分中的数据访问到所述至少两个总线之一，提供对所述至少一个的所述一个部分的访问 存储器，并且路由进一步的数据访问请求，请求从所述数据处理部分接收的所述至少一个存储器的另一部分中的数据访问到所述至少两个总线中的另一个，提供对所述至少一个 存储器，所述数据访问请求的路由在相同的时钟周期期间执行。

公开(公告)号：US07053675B2

公开(公告)日：2006-05-30

申请号：US10626871

申请日：2003-07-25

申请人： Richard Slobodnik ,  Gerard Richard Williams ,  Mark Allen Silla

发明人： Richard Slobodnik ,  Gerard Richard Williams ,  Mark Allen Silla

IPC分类号： G06F1/04

CPC分类号： G06F1/08

摘要： A processor clock control device is disclosed that is operable to control switching between clock signals input to a processor in a glitch-free way. The processor clock control device comprises: at least two clock signal inputs each operable to receive a clock signal, said clock signals comprising a first and a second clock signal; a sensor operable to sense said first and said second clock signals; a clock signal output operable to output a clock signal for input to a processor; and a clock switching signal input for receiving a switching signal operable to control switching of said clock signal output from said first clock signal to said second clock signal; wherein said processor clock control device is operable on receipt of said clock switching signal to sense said first clock signal and when said first clock signal transitions from a first predetermined level to a second level, said processor clock control device is operable to hold said clock signal output at said second level, and then to sense said second clock signal and when said second clock signal transitions from said second level to said first predetermined level to output said second clock signal.

摘要翻译： 公开了一种处理器时钟控制装置，其可操作以控制以无毛刺方式输入到处理器的时钟信号之间的切换。 处理器时钟控制装置包括：至少两个时钟信号输入，每个可操作以接收时钟信号，所述时钟信号包括第一和第二时钟信号; 传感器，其可操作以感测所述第一和所述第二时钟信号; 时钟信号输出，其可操作以输出用于输入到处理器的时钟信号; 以及时钟切换信号输入，用于接收可操作以控制从所述第一时钟信号输出到所述第二时钟信号的所述时钟信号的切换的切换信号; 其中所述处理器时钟控制装置在接收到所述时钟切换信号以操作所述第一时钟信号时可操作，并且当所述第一时钟信号从第一预定电平转变到第二电平时，所述处理器时钟控制装置可操作以保持所述时钟信号 在所述第二电平输出，然后感测所述第二时钟信号，并且当所述第二时钟信号从所述第二电平转换到所述第一预定电平时，输出所述第二时钟信号。

公开(公告)号：US20080222387A1

公开(公告)日：2008-09-11

申请号：US12010512

申请日：2008-01-25

申请人： Barry Duane Williamson ,  Gerard Richard Williams ,  Muralidharan Santharaman Chinnakonda

发明人： Barry Duane Williamson ,  Gerard Richard Williams ,  Muralidharan Santharaman Chinnakonda

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1054 ,  Y02D10/13

摘要： The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access one of said physical address indicators stored within said cache directory corresponding to said indicated storage location and in response to said accessed physical address indicator not indicating said address said data processor is operable to invalidate said indicated storage location within said cache.

摘要翻译： 应用程序描述可操作以处理数据的数据处理器，并且包括：高速缓存，其中通过地址识别所述高速缓存内的数据项的存储位置，所述高速缓存包括多个存储位置，并且所述数据处理器包括高速缓存目录 可操作地存储包括存储的数据的每个存储位置的物理地址指示符; 哈希值发生器，用于从所述地址的所述比特中的至少一些产生生成的散列值，所述哈希值生成的哈希值具有比所述地址少的位; 缓冲器，用于存储与所述高速缓存内的所述多个存储位置相关的多个散列值; 其中响应于访问所述数据项的请求，所述数据处理器可操作以将所生成的散列值与所述缓冲器中存储的所述多个散列值中的至少一些进行比较，并响应于匹配来指示所述数据项的所指示的存储位置 数据项; 并且所述数据处理器可操作以访问存储在与所述指示的存储位置相对应的所述高速缓存目录内的所述物理地址指示符之一，并且响应于所述访问的物理地址指示符不指示所述地址，所述数据处理器可操作以使所述指示的存储位置无效 说缓存。

公开(公告)号：US06782452B2

公开(公告)日：2004-08-24

申请号：US10011310

申请日：2001-12-11

申请人： Gerard Richard Williams, III

发明人： Gerard Richard Williams, III

IPC分类号： G06F1300

CPC分类号： G06F12/0859

摘要： A data processing system includes a processor core, a cache memory and a cache controller which operate to allow data accesses to a cache line for which a pending cache linefill operation exists to be serviced for those data words within the cache line that are valid at a particular point in time. One or more status bits are provided in association with each cache line indicating whether a line fill is pending for that cache line. The old data may be manipulated up to the point where the first new data is returned. New data items may be read once they have been written into a victim cache line even though the cache linefill is not completed. Stores to the victim cache line may be made via a fill buffer even though the linefill is still pending. The cache memory may include a content addressable memory (CAM) and the cache memory and controller may support a hit under miss operation.

摘要翻译： 数据处理系统包括处理器核心，高速缓存存储器和高速缓存控制器，其操作以允许对高速缓存行进行数据访问，对于高速缓存行，存在待定高速缓存行填充操作，以对高速缓存线内的有效的数据字进行服务 特别的时间点。 与每个高速缓存行相关联地提供一个或多个状态位，指示行高速缓存线是否正在等待。 旧的数据可以被操纵直到返回第一个新数据。 即使高速缓存行填充未完成，一旦写入受害者缓存行，新的数据项也可能被读取。 存储到受害者缓存行可以通过填充缓冲区进行，即使该行填充仍在等待。 高速缓冲存储器可以包括内容可寻址存储器（CAM），并且高速缓冲存储器和控制器可以支持在错误操作下的命中。

公开(公告)号：US06552949B1

公开(公告)日：2003-04-22

申请号：US10062567

申请日：2002-02-05

申请人： Mark Allen Silla ,  Arthur R Piejko ,  Michael Louis Brauer ,  Gerard Richard Williams, III

发明人： Mark Allen Silla ,  Arthur R Piejko ,  Michael Louis Brauer ,  Gerard Richard Williams, III

IPC分类号： G11C700

CPC分类号： G11C11/417 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C11/419 ,  G11C2207/2227

摘要： The present invention relates to a memory device and method for reducing leakage current during a power down mode of operation. The memory device comprises a column of memory cells, with each memory cell being arranged to store a data value, and a pair of bit lines coupled to the column of memory cells. Bit line precharge circuitry is provided for precharging the pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in the column is selected in an evaluate phase following the precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell. In accordance with the present invention, the memory device further comprises power down control circuitry arranged when the memory device is to enter a power down mode to prevent the bit line precharge circuitry from precharging the pair of bit lines, and selector circuitry arranged when the memory device is to enter the power down mode to ensure that none of the memory cells in the column are selected. It has been found that by taking this approach during the power down mode of operation, a significant reduction in the leakage current is observed.

摘要翻译： 本发明涉及一种用于在掉电操作模式期间减少泄漏电流的存储器件和方法。 存储器件包括一列存储器单元，每个存储器单元被布置成存储数据值，以及耦合到存储器单元列的一对位线。 位线预充电电路被提供用于在预充电阶段期间将一对位线预充电到预定电压电平，该位位线布置成使得当在预充电之后的评估阶段选择列中的特定存储单元时 一对位线之间的电压电平的相对变化指示存储在所选存储单元内的数据值。 根据本发明，存储器件还包括掉电控制电路，当存储器件要进入掉电模式时被布置，以防止位线预充电电路对该对位线进行预充电;以及选择器电路，当存储器 设备进入掉电模式，以确保列中没有一个存储单元被选中。 已经发现，通过在断电操作模式期间采取该方法，可以观察到泄漏电流的显着降低。

公开(公告)号：US08468405B2

公开(公告)日：2013-06-18

申请号：US12929031

申请日：2010-12-22

申请人： Teresa Louise McLaurin ,  Gerard Richard Williams

发明人： Teresa Louise McLaurin ,  Gerard Richard Williams

IPC分类号： G01R31/28

CPC分类号： G06F11/267

摘要： An integrated circuit 2 provided with multiple functional units 6, 8, 10, 12, 14, and 16 for performing data processing operations as part of advancing execution of a data processing task by the integrated circuit 2. Activity detection circuitry 26 determines which of these functional circuits is inactive at the given time. If a functional is inactive, then scan control circuitry 28 may perform a scan test operation thereon using an associated serial scan chain 34, 36, 38, 40, 42, 44.

摘要翻译： 具有多个功能单元6,8,10,12,14和16的集成电路2，用于执行数据处理操作，作为由集成电路2提前执行数据处理任务的一部分。活动检测电路26确定这些 功能电路在给定的时间无效。 如果功能不活动，则扫描控制电路28可以使用相关联的串行扫描链34,36,38,40,42,44在其上执行扫描测试操作。

公开(公告)号：US07900020B2

公开(公告)日：2011-03-01

申请号：US12010512

申请日：2008-01-25

申请人： Barry Duane Williamson ,  Gerard Richard Williams ,  Muralidharan Santharaman Chinnakonda

发明人： Barry Duane Williamson ,  Gerard Richard Williams ,  Muralidharan Santharaman Chinnakonda

IPC分类号： G06F12/00

CPC分类号： G06F12/0864 ,  G06F12/1054 ,  Y02D10/13

摘要： The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comprising a cache directory operable to store a physical address indicator for each storage location comprising stored data; a hash value generator operable to generate a generated hash value from at least some of said bits of said address said generated hash value having fewer bits than said address; a buffer operable to store a plurality of hash values relating to said plurality of storage locations within said cache; wherein in response to a request to access said data item said data processor is operable to compare said generated hash value with at least some of said plurality of hash values stored within said buffer and in response to a match to indicate a indicated storage location of said data item; and said data processor is operable to access one of said physical address indicators stored within said cache directory corresponding to said indicated storage location and in response to said accessed physical address indicator not indicating said address said data processor is operable to invalidate said indicated storage location within said cache.

摘要翻译： 应用程序描述可操作以处理数据的数据处理器，并且包括：高速缓存，其中通过地址识别所述高速缓存内的数据项的存储位置，所述高速缓存包括多个存储位置，并且所述数据处理器包括高速缓存目录 可操作地存储包括存储的数据的每个存储位置的物理地址指示符; 哈希值发生器，用于从所述地址的所述比特中的至少一些产生生成的散列值，所述哈希值生成的哈希值具有比所述地址少的位; 缓冲器，用于存储与所述高速缓存内的所述多个存储位置相关的多个散列值; 其中响应于访问所述数据项的请求，所述数据处理器可操作以将所生成的散列值与所述缓冲器中存储的所述多个散列值中的至少一些进行比较，并响应于匹配来指示所述数据项的所指示的存储位置 数据项; 并且所述数据处理器可操作以访问存储在与所述指示的存储位置相对应的所述高速缓存目录内的所述物理地址指示符之一，并且响应于所述访问的物理地址指示符不指示所述地址，所述数据处理器可操作以使所述指示的存储位置无效 说缓存。

公开(公告)号：US07254667B2

公开(公告)日：2007-08-07

申请号：US10815982

申请日：2004-04-02

申请人： Tan Ba Tran ,  Richard Roy Grisenthwaite ,  Gerard Richard Williams

发明人： Tan Ba Tran ,  Richard Roy Grisenthwaite ,  Gerard Richard Williams

IPC分类号： G06F12/00

CPC分类号： G06F13/28

摘要： A data processor core 10 comprising a memory access interface portion 30 operable to perform data transfer operations between an external data source and at least one memory associated with said data processor core and a data processing portion 12 operable to perform further data processing operations in response to receipt of said processor clock signal CLK. The two portions of the core being operable to be independently enabled such that one portion may be active while the other is inactive.

摘要翻译： 数据处理器核心10，其包括存储器访问接口部分30，其可操作以在外部数据源与至少一个与所述数据处理器核心相关联的存储器之间执行数据传输操作;以及数据处理部分12，可操作以执行另外的数据处理操作 接收所述处理器时钟信号CLK。 核心的两个部分可操作以独立地启用，使得一个部分可以是活动的，而另一个部分是不活动的。