公开(公告)号：US5150365A

公开(公告)日：1992-09-22

申请号：US548431

申请日：1990-07-05

申请人： Tetsuhiko Hirata ,  Kazuo Yagyu ,  Matsuaki Terada ,  Hiroshi Nakase ,  Shigeru Oshima ,  Motoyoshi Morito ,  Takahiko Nishizawa

发明人： Tetsuhiko Hirata ,  Kazuo Yagyu ,  Matsuaki Terada ,  Hiroshi Nakase ,  Shigeru Oshima ,  Motoyoshi Morito ,  Takahiko Nishizawa

IPC分类号： H04J1/04 ,  H04L12/28 ,  H04N7/10 ,  H04N7/54

CPC分类号： H04N7/10 ,  H04J1/045 ,  H04L12/2801 ,  H04N7/54

摘要： A base-band and broad-band coexisting communication system comprises a transmission path, a plurality of first data terminal units outputting data to be transmitted in the form of pulse signals (base band signals), a plurality of second data terminal units for outputting data to be transmitted in the form of modulated signals (broad band signals) each having a center frequency within a predetermined frequency range, and a plurality of low-pass filters, each connected to each of the first data transmission units, for cutting off high frequency components of the base band signal outputted by the first data terminal device at a predetermined cut-off frequency which does not overlap with the broad band signals.

摘要翻译： 基带和宽带共存通信系统包括传输路径，以脉冲信号（基带信号）的形式输出要发送的数据的多个第一数据终端单元，用于输出数据的多个第二数据终端单元 以每个具有预定频率范围内的中心频率的调制信号（宽带信号）的形式发送，以及多个低通滤波器，每个低通滤波器连接到每个第一数据传输单元，用于切断高频 以与宽带信号不重叠的预定截止频率由第一数据终端装置输出的基带信号的分量。

公开(公告)号：US5377158A

公开(公告)日：1994-12-27

申请号：US190454

申请日：1994-02-02

申请人： Takahiko Nishizawa

发明人： Takahiko Nishizawa

IPC分类号： H03K3/356 ,  G01R31/28 ,  G11C7/10 ,  H03K17/00 ,  G11C8/00

CPC分类号： G11C7/1093 ,  G11C7/1078

摘要： A multi-input memory circuit including a first input gate for selecting one of a plurality of data signals, a first inverting gate for receiving the output of the first input gate as an input, a first feedback gate, which has a structure of a vertical lamination inverter, receives a plurality of clock signals, inverted signals of those clock signals and the output of the first inverting gate, and has its output terminal connected to the output terminal of the first input gate, and a second input gate, which has a vertical lamination inverter structure, and receives a plurality of clock signals, inverted signals of those clock signals and the output of the first input gate, and a second feedback gate, which has a horizontal lamination inverter structure, receives a plurality of clock signals, inverted signals of those clock signals and the output of the second inverting gate, and has its output terminal connected to the output terminal of the second input gate. With this structure, a system of matching the phases of control signals for the individual gates with one another is latently incorporated in the multi-input edge-trigger type memory circuit, thereby preventing data dropout.

摘要翻译： 一种多输入存储器电路，包括用于选择多个数据信号中的一个的第一输入栅极，用于接收第一输入栅极的输出作为输入的第一反相门，具有垂直的结构的第一反馈栅极 层叠逆变器，接收多个时钟信号，这些时钟信号的反相信号和第一反相门的输出，并且其输出端子连接到第一输入栅极的输出端子和第二输入门，其具有 并且接收多个时钟信号，这些时钟信号的反相信号和第一输入栅极的输出，以及具有水平叠层反相器结构的第二反馈栅极接收多个时钟信号，反相 这些时钟信号的信号和第二反向门的输出，并且其输出端连接到第二输入门的输出端。 利用这种结构，将多个各个门的控制信号的相位彼此匹配的系统被潜入并入多输入边沿触发型存储电路中，从而防止数据丢失。