公开(公告)号：US08305134B2

公开(公告)日：2012-11-06

申请号：US12713362

申请日：2010-02-26

申请人： Tetsuya Hirose ,  Toyoaki Kito ,  Yuji Osaki

发明人： Tetsuya Hirose ,  Toyoaki Kito ,  Yuji Osaki

IPC分类号： G05F1/10

CPC分类号： G05F3/242

摘要： A reference current source circuit outputs a constant reference current even if surrounding environments such as temperature and power source voltage change in a power source circuit that operates in a minute current region in an order of nanoamperes. The reference current source circuit includes an nMOS-configured power source circuit, a pMOS-configured power source circuit, and a current subtracter circuit. The nMOS-configured power source circuit includes a current generating nMOSFET, and generates a first current having temperature characteristics of an output current dependent on an electron mobility. The pMOS-configured power source circuit includes a current generating pMOSFET, and generates a second current having temperature characteristics of an output current dependent on a hole mobility. The current subtracter circuit generates a constant reference current by subtracting the second current from the first current.

摘要翻译： 参考电流源电路输出恒定的参考电流，即使在诸如温度和电源电压的周围环境中，在以毫安量级的微小电流区域中操作的电源电路中也会发生变化。 参考电流源电路包括nMOS配置的电源电路，pMOS配置的电源电路和电流减法器电路。 nMOS配置的电源电路包括电流产生nMOSFET，并且产生具有取决于电子迁移率的输出电流的温度特性的第一电流。 pMOS配置的电源电路包括电流产生pMOSFET，并且产生具有取决于空穴迁移率的输出电流的温度特性的第二电流。 电流减法器电路通过从第一电流中减去第二电流来产生恒定的参考电流。

公开(公告)号：US08421435B2

公开(公告)日：2013-04-16

申请号：US12713372

申请日：2010-02-26

申请人： Tetsuya Hirose ,  Yuji Osaki ,  Kei Matsumoto

发明人： Tetsuya Hirose ,  Yuji Osaki ,  Kei Matsumoto

IPC分类号： G05F3/16

CPC分类号： G05F3/242

摘要： In a circuit and method for correcting a delay variation of a subthreshold CMOS circuit operating in a subthreshold region, a power supply voltage controlling circuit is provided for supplying a controlled output voltage to a subthreshold digital CMOS circuit as a controlled power supply voltage. The subthreshold digital CMOS circuit includes CMOS circuits each having a pMOSFET and an nMOSFET and operating in a subthreshold region with a predetermined delay time, and further includes a minute current generator circuit generating a predetermined minute current based on a power supply voltage, and a controlled output voltage generator circuit generating a controlled output voltage for correcting a variation in the delay time based on a generated minute current and supplying the controlled output voltage to the subthreshold digital CMOS circuit as a controlled power supply voltage including a change in each threshold voltage of the pMOSFET and the nMOSFET.

摘要翻译： 在用于校正在亚阈值区域中工作的亚阈值CMOS电路的延迟变化的电路和方法中，提供电源电压控制电路，用于将受控输出电压作为受控电源电压提供给次阈值数字CMOS电路。 亚阈值数字CMOS电路包括各自具有pMOSFET和nMOSFET并且在具有预定延迟时间的亚阈值区域中操作的CMOS电路，并且还包括基于电源电压产生预定微小电流的微小电流发生器电路，以及受控 输出电压发生器电路产生受控的输出电压，用于基于产生的微小电流来校正延迟时间的变化，并将受控输出电压提供给次阈值数字CMOS电路作为受控电源电压，该受控电源电压包括每个阈值电压的变化 pMOSFET和nMOSFET。

公开(公告)号：US20130049875A1

公开(公告)日：2013-02-28

申请号：US13591340

申请日：2012-08-22

申请人： Seichiro SHIGA ,  Tetsuya Hirose ,  Yuji Osaki

发明人： Seichiro SHIGA ,  Tetsuya Hirose ,  Yuji Osaki

IPC分类号： H03K3/02

CPC分类号： H03K3/354 ,  H03K3/011 ,  H03K5/1515

摘要： A control circuit controls first and second clock generator subcircuits so that one subcircuit of the first and second clock generator subcircuits operates for a comparison voltage generating interval, then another subcircuit operates for a clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the comparison voltage generating interval and the clock generating interval. For the comparison voltage generating interval, each of the first and second clock generator subcircuits is controlled to generate a comparison voltage and output the same voltage to an inverted output terminal of a comparator. For the clock generating interval, each of the first and second clock generator subcircuits compares an output voltage from a current-voltage converter circuit with the comparison voltage.

摘要翻译： 控制电路控制第一和第二时钟发生器子电路，使得第一和第二时钟发生器子电路的一个子电路用于比较电压产生间隔，然后另一个子电路用于时钟产生间隔，并且使得第一和第二时钟发生器子电路 交替重复比较电压产生间隔和时钟产生间隔的处理。 对于比较电压产生间隔，控制第一和第二时钟发生器子电路中的每一个以产生比较电压并将相同的电压输出到比较器的反相输出端。 对于时钟产生间隔，第一和第二时钟发生器子电路中的每一个将电流 - 电压转换器电路的输出电压与比较电压进行比较。

公开(公告)号：US08692623B2

公开(公告)日：2014-04-08

申请号：US13591340

申请日：2012-08-22

申请人： Seichiro Shiga ,  Tetsuya Hirose ,  Yuji Osaki

发明人： Seichiro Shiga ,  Tetsuya Hirose ,  Yuji Osaki

IPC分类号： H03K3/0231

CPC分类号： H03K3/354 ,  H03K3/011 ,  H03K5/1515

摘要： A control circuit controls first and second clock generator subcircuits so that one subcircuit of the first and second clock generator subcircuits operates for a comparison voltage generating interval, then another subcircuit operates for a clock generating interval, and so that the first and second clock generator subcircuits alternately repeat processes of the comparison voltage generating interval and the clock generating interval. For the comparison voltage generating interval, each of the first and second clock generator subcircuits is controlled to generate a comparison voltage and output the same voltage to an inverted output terminal of a comparator. For the clock generating interval, each of the first and second clock generator subcircuits compares an output voltage from a current-voltage converter circuit with the comparison voltage.

摘要翻译： 控制电路控制第一和第二时钟发生器子电路，使得第一和第二时钟发生器子电路的一个子电路用于比较电压产生间隔，然后另一个子电路用于时钟产生间隔，并且使得第一和第二时钟发生器子电路 交替地重复比较电压产生间隔和时钟产生间隔的处理。 对于比较电压产生间隔，控制第一和第二时钟发生器子电路中的每一个以产生比较电压并将相同的电压输出到比较器的反相输出端。 对于时钟产生间隔，第一和第二时钟发生器子电路中的每一个将电流 - 电压转换器电路的输出电压与比较电压进行比较。

公开(公告)号：US20120025801A1

公开(公告)日：2012-02-02

申请号：US13192854

申请日：2011-07-28

申请人： Tetsuya HIROSE ,  Yuji Osaki

发明人： Tetsuya HIROSE ,  Yuji Osaki

IPC分类号： G05F3/16

CPC分类号： G05F3/242

摘要： A MOS resistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS resistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS resistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS resistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of adding results to the drain of the MOS resistor as the drain bias voltage.

摘要翻译： MOS电阻基于在漏极及其源极上感应的电压产生输出电流。 栅极偏置电压发生器电路产生栅极偏置电压，以在强反转线性区域中操作MOS电阻器，并将栅极偏置电压施加到MOS电阻器的栅极。 漏极偏置电压发生器电路产生漏极偏置电压，并将漏极偏置电压施加到MOS电阻器的漏极。 添加的偏置电压发生器电路产生具有预定温度系数并且包括预定偏移电压的附加偏置电压，使得输出电流随着温度变化而变得恒定。 漏极偏置电压发生器电路将添加的偏置电压加到漏极偏置电压，并且将施加结果的电压作为漏极偏置电压施加到MOS电阻器的漏极。

公开(公告)号：US08614570B2

公开(公告)日：2013-12-24

申请号：US13192854

申请日：2011-07-28

申请人： Tetsuya Hirose ,  Yuji Osaki

发明人： Tetsuya Hirose ,  Yuji Osaki

IPC分类号： G05F3/16 ,  G05F1/10

CPC分类号： G05F3/242

摘要： A MOS transistor generates an output current based on a voltage induced across a drain and a source thereof. A gate bias voltage generator circuit generates a gate bias voltage so as to operate the MOS transistor in a strong-inversion linear region, and applies the gate bias voltage to a gate of the MOS transistor. A drain bias voltage generator circuit generates a drain bias voltage, and applies the drain bias voltage to the drain of the MOS transistor. An added bias voltage generator circuit generates an added bias voltage, which has a predetermined temperature coefficient and includes a predetermined offset voltage, so that the output current becomes constant against temperature changes. The drain bias voltage generator circuit adds the added bias voltage to the drain bias voltage, and applies a voltage of the adding results to the drain of the MOS transistor as the drain bias voltage.

摘要翻译： MOS晶体管基于在漏极及其源极上感应的电压产生输出电流。 栅极偏置电压发生器电路产生栅极偏置电压，以便在强反转线性区域中操作MOS晶体管，并且将栅极偏置电压施加到MOS晶体管的栅极。 漏极偏置电压发生器电路产生漏极偏置电压，并将漏极偏置电压施加到MOS晶体管的漏极。 添加的偏置电压发生器电路产生具有预定温度系数并且包括预定偏移电压的附加偏置电压，使得输出电流随着温度变化而变得恒定。 漏极偏置电压发生器电路将添加的偏置电压加到漏极偏置电压，并将加法结果的电压作为漏极偏置电压施加到MOS晶体管的漏极。

公开(公告)号：US08436654B2

公开(公告)日：2013-05-07

申请号：US13181825

申请日：2011-07-13

申请人： Tetsuya Hirose ,  Yuji Osaki ,  Toshihiko Mori

发明人： Tetsuya Hirose ,  Yuji Osaki ,  Toshihiko Mori

IPC分类号： H03K19/0175

CPC分类号： H03K19/018521

摘要： A level converter circuit is provided for converting an input signal of a digital signal having a first signal level into an output signal having a second signal level higher than the first signal level. An amplifier circuit amplifies the input signal and outputs an amplified output signal, and a current generator circuit generates a control current corresponding to an operating current flowing through the amplifier circuit upon change of the signal level of the input signal. A current detector circuit detects the generated control current, and controls the operating current of the amplifier circuit to correspond to the detected control current. The current generator circuit includes series-connected first and second nMOS transistors as inserted between the current detector circuit and the ground. The first nMOS transistor operates responsive to the input signal, and the second nMOS transistor operates responsive to an inverted signal of the input signal.

摘要翻译： 提供电平转换器电路，用于将具有第一信号电平的数字信号的输入信号转换为具有高于第一信号电平的第二信号电平的输出信号。 放大器电路放大输入信号并输出​​放大的输出信号，并且电流发生器电路在输入信号的信号电平改变时产生对应于流过放大器电路的工作电流的控制电流。 电流检测器电路检测所产生的控制电流，并且控制放大器电路的工作电流对应于检测到的控制电流。 电流发生器电路包括插入电流检测器电路和地之间的串联连接的第一和第二nMOS晶体管。 第一nMOS晶体管响应于输入信号而工作，并且第二nMOS晶体管响应输入信号的反相信号而工作。