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    Image slicing to generate in put frames for a digital micromirror device
    1.
    发明授权
    Image slicing to generate in put frames for a digital micromirror device 有权

    公开(公告)号：US11496720B2

    公开(公告)日：2022-11-08

    申请号：US17545876

    申请日：2021-12-08

    Applicant: Texas Instruments Incorporated

    Inventor： Daniel Jay Morgan ,  Aravind Lakshminarayanan ,  Vivek Kumar Thakur

    IPC: H04N9/31

    Abstract: Example apparatus described herein include a first circuit configured to slice an input image frame into input image slices, the first circuit including first outputs configured to output the input image slices. Described example apparatus also include digital light processing controllers (DLPCs) including first inputs coupled to the first outputs, the digital light processing controllers configured to process the input image slices to produce output image slices, the digital light processing controllers including second outputs configured to output the output image slices. Described example apparatus further include a second circuit including second inputs coupled to the second outputs, the second circuit configured to combine the output image slices to generate image frame data to provide to an input of a digital micromirror device (DMD).

    Increased bit depth in high frame rate applications
    2.
    发明授权
    Increased bit depth in high frame rate applications 有权

    公开(公告)号：US11314081B2

    公开(公告)日：2022-04-26

    申请号：US16425588

    申请日：2019-05-29

    Applicant: Texas Instruments Incorporated

    Inventor： Aravind Lakshminarayanan ,  Daniel J. Morgan

    IPC: G02B27/00 ,  G02B27/01 ,  G09G3/34 ,  G09G3/20

    Abstract: Described examples include a process that includes illuminating a spatial light modulator at a first illumination level during a first bit-plane and stopping illumination at a beginning of a second bit-plane subsequent to the first bit-plane. The process also includes resuming illumination after a settling period of the spatial light modulator at a second illumination level for a time period such that a total illumination energy during the second bit-plane is equivalent to an intended illumination energy for the second bit-plane at the first illumination level and stopping illumination at the second illumination level before a subsequent third bit-plane.

    BIT PLANE DITHERING APPARATUS
    3.
    发明申请
    BIT PLANE DITHERING APPARATUS 有权

    公开(公告)号：US20240371342A1

    公开(公告)日：2024-11-07

    申请号：US18775893

    申请日：2024-07-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jeffrey Kempf ,  Aravind Lakshminarayanan ,  Jonathan Lucas

    IPC: G09G5/02

    Abstract: A system, includes a controller configured to obtain, for an image frame stored in a frame memory image, data associated with a color component and generate dithered bit planes having a dither noise pattern, the dithered bit planes including time repeated bit plane sequences in the image frame. The system also includes a spatial light modulator (SLM) coupled to the controller. The SLM is configured to project an image of the image frame according to the dithered bit planes. Additionally, the system includes a light source optically coupled to the SLM. The light source is configured to provide light for projecting the image.

    Extending operational lifetime of spatial light modulator devices with content-dependent encoding
    5.
    发明授权
    Extending operational lifetime of spatial light modulator devices with content-dependent encoding 有权

    公开(公告)号：US11074074B2

    公开(公告)日：2021-07-27

    申请号：US16291873

    申请日：2019-03-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Aravind Lakshminarayanan ,  Vivek Kumar Thakur

    IPC: G06F9/30 ,  H03K7/08 ,  H03K5/156 ,  H04N9/31

    Abstract: This disclosure relates to various implementations improve operational lifetime for a spatial light modulator device. One or more controllers are able to determine a target duty cycle based on an operating condition for a spatial light modulator device. The spatial light modulator device comprises one or more light modulation components that modulate light. The controllers allocate a refresh time period for encoding spatial light modulator refresh instructions based on the target duty cycle and encode spatial light modulator refresh instructions within the refresh time period. Afterwards, the controllers transmit the spatial light modulator refresh instruction to the spatial light modulator device.

    Bit plane dithering apparatus
    6.
    发明授权
    Bit plane dithering apparatus 有权

    公开(公告)号：US12067956B2

    公开(公告)日：2024-08-20

    申请号：US17683128

    申请日：2022-02-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jeffrey Matthew Kempf ,  Aravind Lakshminarayanan ,  Jonathan Lucas

    IPC: G06T1/60 ,  G09G5/02

    CPC classification number: G09G5/022 ,  G09G2320/0285 ,  G09G2360/123

    Abstract: A controller includes a frame memory configured to store an image frame, a frame memory controller coupled to the frame memory and configured to obtain image data from the image frame. The image data is associated with a color component of the image frame. The controller also includes a dither noise mask generator configured to provide dither noise masks according to dither noise levels for the image data, and a bit plane generator coupled to the frame memory controller and the dither noise mask generator and configured to generate bit planes based on the dither noise masks for the image data.

    Spatial light modulator control
    8.
    发明授权
    Spatial light modulator control 有权

    公开(公告)号：US11159773B1

    公开(公告)日：2021-10-26

    申请号：US17119277

    申请日：2020-12-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Aravind Lakshminarayanan ,  Daniel J. Morgan

    IPC: H04N9/31

    Abstract: A control circuit includes a sequencing circuit. The sequencing circuit is configured to, in a color cycle: transfer a first bit plane to a spatial light modulator (SLM) and transmit a first global reset signal to the SLM instructing the SLM to load data of the first bit plane to pixel sub arrays of the SLM. The sequencing circuit is also configured to, in the color cycle: transfer a second bit plane to the SLM, and transmit a second global reset signal instructing the SLM to load data of the second bit plane to a first pixel sub-array of the pixel sub-arrays and to load data of the first bit plane to a second pixel sub-array of the pixel sub-arrays.

    Multi-channel display systems
    9.
    发明授权
    Multi-channel display systems 有权

    公开(公告)号：US11778135B2

    公开(公告)日：2023-10-03

    申请号：US17119820

    申请日：2020-12-11

    Applicant: Texas Instruments Incorporated

    Inventor： Aravind Lakshminarayanan ,  Vivek Kumar Thakur ,  Jobin Raj

    IPC: H04N5/45 ,  G06F3/14 ,  H04N5/04

    CPC classification number: H04N5/45 ,  G06F3/1423 ,  H04N5/04

    Abstract: Example multi-channel display systems are disclosed. An example apparatus includes at least one processor to execute instructions to at least in response to determining that a first display controller is to provide at least a first portion of video data on a first channel, provide a first control signal to the first display controller instructing the first display controller to provide the at least the first portion of the video data on the first channel, and in response to determining that a second display controller is to provide at least a second portion of the video data on a second channel, provide a second control signal to the second display controller instructing the second display controller to provide the at least the second portion of the video data on the second channel, the second channel different from the first channel.

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