公开(公告)号：US08748996B2

公开(公告)日：2014-06-10

申请号：US13862581

申请日：2013-04-15

Applicant: Texas Instruments Incorporated

Inventor： James Joseph Chambers ,  Hiroaki Niimi ,  Brian Keith Kirkpatrick

IPC: H01L21/02

CPC classification number: H01L29/78 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of 10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ≧2 atomic % less than a peak N concentration of the bulk portion.

Abstract translation: 集成电路（IC）包括具有顶部半导体表面的衬底，该顶部半导体表面包括至少一个MOS器件，其包括间隔开的源极和漏极区域以限定沟道区域。 在顶部半导体表面上形成具有多个不同N个浓度部分的SiON栅介质层。 栅电极位于SiON层上。 多个不同的N个浓度部分包括（i）平均N浓度<2原子％延伸到半导体界面的底部，（ii）平均N浓度> 10原子％的本体部分，和（iii） 本体部分的顶部延伸到具有比本体部分的峰值N浓度小2％原子％的平均N浓度的栅电极界面。