公开(公告)号：US20140187009A1

公开(公告)日：2014-07-03

申请号：US14142075

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/311 ,  H01L29/66

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.

Abstract translation: 可以通过形成牺牲氮化硅特征来形成集成电路。 牺牲氮化硅特征的至少一部分可以通过将集成电路放置在两步氧化层蚀刻工具中并且使用两步蚀刻工艺从牺牲氮化硅特征中除去氧化硅的表面层来去除。 两步蚀刻工艺将集成电路暴露于等离子体源的温度低于40℃的反应物，随后将集成电路加热至80℃至120℃，同时在两步氧化层蚀刻 工具。 当集成电路处于两步氧化层蚀刻工具中时，不将集成电路暴露于含有超过1托的氧的环境中，使用含氟蚀刻剂除去至少一部分牺牲氮化硅特征， 基本上不含氨。

公开(公告)号：US09437449B2

公开(公告)日：2016-09-06

申请号：US14142075

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.

Abstract translation: 可以通过形成牺牲氮化硅特征来形成集成电路。 牺牲氮化硅特征的至少一部分可以通过将集成电路放置在两步氧化层蚀刻工具中并且使用两步蚀刻工艺从牺牲氮化硅特征中去除氧化硅的表面层来去除。 两步蚀刻工艺将集成电路暴露于等离子体源的温度低于40℃的反应物，随后将集成电路加热至80℃至120℃，同时在两步氧化层蚀刻 工具。 当集成电路处于两步氧化层蚀刻工具中时，不将集成电路暴露于含有超过1托的氧的环境中，使用含氟蚀刻剂除去至少一部分牺牲氮化硅特征， 基本上不含氨。

公开(公告)号：US20160343581A1

公开(公告)日：2016-11-24

申请号：US15228204

申请日：2016-08-04

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.

Abstract translation: 可以通过形成牺牲氮化硅特征来形成集成电路。 牺牲氮化硅特征的至少一部分可以通过将集成电路放置在两步氧化层蚀刻工具中并且使用两步蚀刻工艺从牺牲氮化硅特征中去除氧化硅的表面层来去除。 两步蚀刻工艺将集成电路暴露于等离子体源的温度低于40℃的反应物，随后将集成电路加热至80℃至120℃，同时在两步氧化层蚀刻 工具。 当集成电路处于两步氧化层蚀刻工具中时，不将集成电路暴露于含有超过1托的氧的环境中，使用含氟蚀刻剂除去至少一部分牺牲氮化硅特征， 基本上不含氨。

公开(公告)号：US20150187661A1

公开(公告)日：2015-07-02

申请号：US14575512

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/823814

Abstract: A process for forming an integrated circuit with an embedded epitaxially grown semiconductor using an epi blocking bilayer. The epi blocking bilayer comprised of a two different materials that may be etched selectively with respect to each other such as silicon nitride and silicon dioxide.

Abstract translation: 使用外延阻挡双层形成具有嵌入式外延生长半导体的集成电路的工艺。 外延阻挡双层由可相对于彼此选择性地蚀刻的两种不同材料组成，例如氮化硅和二氧化硅。

公开(公告)号：US09704720B2

公开(公告)日：2017-07-11

申请号：US15228204

申请日：2016-08-04

Applicant: Texas Instruments Incorporated

Inventor： Tom Lii ,  David Farber

IPC: H01L21/311 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01J37/32357 ,  H01L21/0217 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: An integrated circuit may be formed by forming a sacrificial silicon nitride feature. At least a portion of the sacrificial silicon nitride feature may be removed by placing the integrated circuit in a two-step oxidized layer etch tool and removing a surface layer of oxidized silicon from the sacrificial silicon nitride feature using a two-step etch process. The two-step etch process exposes the integrated circuits to reactants from a plasma source at a temperature less than 40° C. and subsequently heating the integrated circuit to 80° C. to 120° C. while in the two-step oxidized layer etch tool. While the integrated circuit is in the two-step oxidized layer etch tool, without exposing the integrated circuit to an ambient containing more than 1 torr of oxygen, at least a portion of the sacrificial silicon nitride feature is removed using fluorine-containing etch reagents, substantially free of ammonia.