公开(公告)号：US20240320092A1

公开(公告)日：2024-09-26

申请号：US18678308

申请日：2024-05-30

Applicant: Texas Instruments Incorporated

Inventor： Saya Goud Langadi ,  David Peter Foley

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F13/1631 ,  G06F13/1668

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

公开(公告)号：US12032440B2

公开(公告)日：2024-07-09

申请号：US17866659

申请日：2022-07-18

Applicant: Texas Instruments Incorporated

Inventor： Saya Goud Langadi ,  David Peter Foley

IPC: G11C29/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/30 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F13/1631 ,  G06F13/1668

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

公开(公告)号：US11055172B2

公开(公告)日：2021-07-06

申请号：US16153546

申请日：2018-10-05

Applicant: Texas Instruments Incorporated

Inventor： David Peter Foley

IPC: G06F11/10 ,  G06F11/07

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.

公开(公告)号：US20170123811A1

公开(公告)日：2017-05-04

申请号：US15178778

申请日：2016-06-10

Applicant: Texas Instruments Incorporated

Inventor： David Peter Foley ,  Santosh Kumar Athuru

IPC: G06F9/44

CPC classification number: G06F9/441 ,  G06F1/3203 ,  G06F9/445

Abstract: An integrated circuit (IC) chip and method of booting the IC are disclosed. The method includes determining whether a boot pin configuration has been programmed and responsive to determining that the boot pin configuration has been programmed, performing a boot method indicated in a user-defined boot table. Responsive to determining that the boot pin configuration key has not been programmed, the method performs a boot method selected from a factory-defined boot table.

公开(公告)号：US20220350699A1

公开(公告)日：2022-11-03

申请号：US17866659

申请日：2022-07-18

Applicant: Texas Instruments Incorporated

Inventor： Saya Goud Langadi ,  David Peter Foley

IPC: G06F11/10 ,  G06F11/07 ,  G06F13/16 ,  G06F11/30

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

公开(公告)号：US10459735B2

公开(公告)日：2019-10-29

申请号：US15178778

申请日：2016-06-10

Applicant: Texas Instruments Incorporated

Inventor： David Peter Foley ,  Santosh Kumar Athuru

IPC: G06F9/4401 ,  G06F9/445 ,  G06F1/3203

Abstract: An integrated circuit (IC) chip and method of booting the IC are disclosed. The method includes determining whether a boot pin configuration has been programmed and responsive to determining that the boot pin configuration has been programmed, performing a boot method indicated in a user-defined boot table. Responsive to determining that the boot pin configuration key has not been programmed, the method performs a boot method selected from a factory-defined boot table.