公开(公告)号：US20160027888A1

公开(公告)日：2016-01-28

申请号：US14875343

申请日：2015-10-05

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. EKBOTE ,  Kwan-Yong LIM ,  Ebenezer ESHUN ,  Youn Sung CHOI

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/417 ,  H01L27/02 ,  H01L29/08 ,  H01L27/088 ,  H01L29/161

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

公开(公告)号：US20150187656A1

公开(公告)日：2015-07-02

申请号：US14576769

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Younsung CHOI ,  Kwan-Yong LIM ,  Ebenezer ESHUN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L21/324 ,  H01L21/268

CPC classification number: H01L21/0217 ,  H01L21/265 ,  H01L21/268 ,  H01L21/324 ,  H01L29/7847

Abstract: An integrated circuit with reduced gate induced drain leakage and with reduced reverse biased diode leakage is formed using a process that employs a first laser anneal, a rapid thermal anneal, and a second laser anneal after implanting the source and drain dopant to improve transistor performance.

Abstract translation: 使用采用第一激光退火，快速热退火和注入源极和漏极掺杂剂以提高晶体管性能的第二激光退火的工艺，形成具有减小的栅极引起的漏极泄漏和减小的反向偏置二极管泄漏的集成电路。

公开(公告)号：US20150287801A1

公开(公告)日：2015-10-08

申请号：US14744384

申请日：2015-06-19

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. EKBOTE ,  Kwan-Yong LIM ,  Ebenezer ESHUN ,  Youn Sung CHOI

IPC: H01L29/45 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract translation: 集成电路包括PMOS栅极结构和相邻场氧化物上的栅极结构。 在场氧化物上的栅极结构上形成外延硬掩模，使得外延硬掩模与PMOS源极/漏极区域中的半导体材料重叠。 SiGe半导体材料在源极/漏极区域中外延形成，使得在场氧化物处的SiGe半导体材料的顶部边缘不超过邻接该场的源极/漏极区域中的SiGe的深度的三分之一以上 氧化物。 场氧化物上的栅极结构的侧表面上的介电隔离物延伸到SiGe上; 至少有三分之一的SiGe被暴露。 金属硅化物覆盖SiGe的顶表面的至少三分之一。 触点具有触点底部的至少一半直接接触SiGe上的金属硅化物。

公开(公告)号：US20150054084A1

公开(公告)日：2015-02-26

申请号：US13972973

申请日：2013-08-22

Applicant: Texas Instruments Incorporated

Inventor： Shashank S. EKBOTE ,  Kwan-Yong LIM ,  Ebenezer ESHUN ,  Youn Sung CHOI

IPC: H01L27/088 ,  H01L29/66

CPC classification number: H01L29/45 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract translation: 集成电路包括PMOS栅极结构和相邻场氧化物上的栅极结构。 在场氧化物上的栅极结构上形成外延硬掩模，使得外延硬掩模与PMOS源极/漏极区域中的半导体材料重叠。 SiGe半导体材料在源极/漏极区域中外延形成，使得在场氧化物处的SiGe半导体材料的顶部边缘不超过邻接该场的源极/漏极区域中的SiGe的深度的三分之一以上 氧化物。 场氧化物上的栅极结构的侧表面上的介电隔离物延伸到SiGe上; 至少有三分之一的SiGe被暴露。 金属硅化物覆盖SiGe的顶表面的至少三分之一。 触点具有触点底部的至少一半直接接触SiGe上的金属硅化物。

公开(公告)号：US20150270174A1

公开(公告)日：2015-09-24

申请号：US14726691

申请日：2015-06-01

Applicant: Texas Instruments Incorporated

Inventor： Himadri Sekhar PAL ,  Ebenezer ESHUN ,  Shashank S. EKBOTE

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/265 ,  H01L27/11

CPC classification number: H01L21/823425 ,  H01L21/26513 ,  H01L21/311 ,  H01L21/823412 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/20 ,  H01L29/66477

Abstract: In an integrated circuit that includes an NMOS logic transistor, an NMOS SRAM transistor, and a resistor, the gate of the SRAM transistor is doped at the same time that the resistor is doped, thereby allowing the gate of the logic transistor to be separately doped without requiring any additional masking steps.

Abstract translation: 在包括NMOS逻辑晶体管，NMOS SRAM晶体管和电阻器的集成电路中，在掺杂电阻器的同时掺杂SRAM晶体管的栅极，从而允许逻辑晶体管的栅极被单独掺杂 而不需要任何额外的掩蔽步骤。