公开(公告)号：US10107841B2

公开(公告)日：2018-10-23

申请号：US15172403

申请日：2016-06-03

Applicant: Texas Instruments Incorporated

Inventor： Viktor Tasevski ,  Kemal S. Demirci

IPC: H02M1/08 ,  G01R19/04

Abstract: In described examples, an apparatus includes: an input terminal for receiving an alternating current voltage signal; a clamping circuit coupled to the input terminal outputting a clamped voltage signal that is constrained in magnitude; a first comparator coupled to the clamped voltage signal outputting a first compare signal when the clamped voltage signal is a positive voltage that exceeds a positive threshold; and a second comparator coupled to the clamped voltage signal outputting a second compare signal when the clamped voltage signal is a negative voltage that exceeds a negative threshold. The apparatus includes a timer circuit coupled to the first and second compare signal outputting a time duration signal corresponding to a time between the first and second compare signals; and a logic circuit coupled to the time duration output signal determining a peak voltage of the alternative current voltage signal responsive to the time duration output signal.

公开(公告)号：US20170023621A1

公开(公告)日：2017-01-26

申请号：US15172403

申请日：2016-06-03

Applicant: Texas Instruments Incorporated

Inventor： Viktor Tasevski ,  Kemal S. Demirci

IPC: G01R19/04

CPC classification number: G01R19/04

Abstract: In described examples, an apparatus includes: an input terminal for receiving an alternating current voltage signal; a clamping circuit coupled to the input terminal outputting a clamped voltage signal that is constrained in magnitude; a first comparator coupled to the clamped voltage signal outputting a first compare signal when the clamped voltage signal is a positive voltage that exceeds a positive threshold; and a second comparator coupled to the clamped voltage signal outputting a second compare signal when the clamped voltage signal is a negative voltage that exceeds a negative threshold. The apparatus includes a timer circuit coupled to the first and second compare signal outputting a time duration signal corresponding to a time between the first and second compare signals; and a logic circuit coupled to the time duration output signal determining a peak voltage of the alternative current voltage signal responsive to the time duration output signal.

Abstract translation: 在上述例子中，一种装置包括：一个用于接收交流电压信号的输入端; 耦合到输入端子的钳位电路输出被限制在大小上的钳位电压信号; 耦合到所述钳位电压信号的第一比较器，当所述钳位的电压信号是超过正阈值的正电压时，输出第一比较信号; 以及耦合到所述钳位电压信号的第二比较器，当所述钳位的电压信号是超过负阈值的负电压时，所述第二比较器输出第二比较信号。 该装置包括一个与第一和第二比较信号耦合的定时器电路，输出对应于第一和第二比较信号之间的时间的持续时间信号; 以及逻辑电路，其耦合到所述持续时间输出信号，以响应于所述持续时间输出信号确定所述备选电流电压信号的峰值电压。

公开(公告)号：US08975963B2

公开(公告)日：2015-03-10

申请号：US13835264

申请日：2013-03-15

Applicant: Texas Instruments Incorporated

Inventor： Ajit Sharma ,  Kemal S. Demirci

IPC: H03F3/45

CPC classification number: H03F3/45076 ,  H03F3/45475 ,  H03F3/45973 ,  H03F2203/45138 ,  H03F2203/45212 ,  H03F2203/45522 ,  H03F2203/45526

Abstract: A circuit includes a first amplifier configured to amplify an input signal to generate an output signal. An offset sensor is configured to sense DC offset based on the output signal, where the offset sensor includes a second amplifier configured to generate an offset reduction signal for the first amplifier based on the sensed DC offset. A T-network in the circuit includes at least three resistors coupled to provide a feedback connection between the input signal and the output signal for the first amplifier and to receive the offset reduction signal to mitigate DC offset in the first amplifier. Since this method reduces the low-frequency component of the signal, it also shapes and reduces the flicker noise.

Abstract translation: 电路包括被配置为放大输入信号以产生输出信号的第一放大器。 偏移传感器被配置为基于输出信号感测DC偏移，其中偏移传感器包括被配置为基于感测的DC偏移产生用于第一放大器的偏移减小信号的第二放大器。 电路中的T网络包括至少三个电阻器，其被耦合以在第一放大器的输入信号和输出信号之间提供反馈连接，并且接收偏移降低信号以减轻第一放大器中的DC偏移。 由于该方法降低了信号的低频分量，因此也可以形成和减少闪烁噪声。