IN-LINE CHROMATIC ABERRATION CORRECTION IN WIDE DYNAMIC RANGE (WDR) IMAGE PROCESSING PIPELINE

    公开(公告)号:US20230336887A1

    公开(公告)日:2023-10-19

    申请号:US18343018

    申请日:2023-06-28

    摘要: In an advanced driver-assistance system (ADAS), RAW sensor image processing for a machine vision (MV) application is important. Due to different color, e.g., red/green/blue (RGB), color components, being focused by the lens at different locations in image plane, the lateral chromatic aberration phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) components. An in-pipeline CAC design may be used to perform on-the-fly CAC without any out-of-pipeline memory traffic; enable use of wide dynamic range (WDR) sensors; uses bicubic interpolation; support vertical and horizontal chromatic aberration color channel offsets, reduce CAC line memory requirements, and support flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.

    IN-LINE CHROMATIC ABERRATION CORRECTION IN WIDE DYNAMIC RANGE (WDR) IMAGE PROCESSING PIPELINE

    公开(公告)号:US20230199339A1

    公开(公告)日:2023-06-22

    申请号:US17555145

    申请日:2021-12-17

    IPC分类号: H04N9/04 G06T1/60 G06T3/40

    摘要: In the advanced driver-assistance systems (ADAS) field, RAW sensor image processing for machine vision (MV) applications can be of critical importance. Due to red/green/blue (RGB) image components being focused by the lens at different locations in image plane, the lateral chromatic aberration (LCA) phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) modules. In some embodiments, an in-pipeline CAC design is used that: is configured to perform on-the-fly CAC without any out-of-pipeline memory traffic; enables use of wide dynamic range (WDR) sensors; uses bicubic interpolation; supports vertical and horizontal chromatic aberration red/blue color channel offsets, reduces CAC line memory requirements, and supports flexible look-up table (LUT) down-sampling factors to improve the spatial precision of correction and accommodate popular image sensor resolutions.

    GLOBAL TIME COUNTER BASED DEBUG
    3.
    发明申请

    公开(公告)号:US20230115615A1

    公开(公告)日:2023-04-13

    申请号:US17486675

    申请日:2021-09-27

    IPC分类号: G01R31/3177 G06F1/10

    摘要: Techniques for debugging a circuit including a global counter configured to continuously increment, a comparator configured to transmit a clock stop signal based on a comparison of a comparator value and a counter value of the global counter, and clock stop circuitry configured to receive the clock stop signal and stop a clock signal to one or more portions of the electronic device.