公开(公告)号：US20140082576A1

公开(公告)日：2014-03-20

申请号：US14028834

申请日：2013-09-17

Applicant: Texas Instruments Incorporated

Inventor： Raashid Moin Shaikh ,  Vishnuraj Arukat Rajan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/84

Abstract: A method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select, placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist. The derate value for a predetermined number of circuit path depths below k are identical. The derate values are monotonically decreasing for increasing circuit depths in a range between 1.0 and 1.5. Separate timing model tables with differing identical values can be employed for standard and clock tree cells.

Abstract translation: 一种制造半导体电路的方法是使用每个单元的延迟来寻找预先选择的，放置的和路由的单元组的定时闭合，该延迟是由从具有对应于所述电路路径深度的降额值的定时模型表获得的降额值降低的 网表。 预定数量的电路路径深度低于k的降额值是相同的。 在1.0和1.5之间的范围内增加电路深度时，降额值单调递减。 可以对标准和时钟树单元采用具有不同相同值的单独时序模型表。

公开(公告)号：US11333707B2

公开(公告)日：2022-05-17

申请号：US16703909

申请日：2019-12-05

Applicant: Texas Instruments Incorporated

Inventor： Khushboo Agarwal ,  Sanjay Krishna Hulical Vijayaraghavachar ,  Raashid Moin Shaikh ,  Srivaths Ravi ,  Wilson Pradeep ,  Rajesh Kumar Tiwari

IPC: G06F30/33 ,  G01R31/317

Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

公开(公告)号：US09449137B2

公开(公告)日：2016-09-20

申请号：US14028811

申请日：2013-09-17

Applicant: Texas Instruments Incorporated

Inventor： Raashid Moin Shaikh ,  Vishnuraj Arukat Rajan

IPC: G06F13/36 ,  G06F17/50 ,  G06F13/40

CPC classification number: G06F17/5081 ,  G06F13/4027 ,  G06F17/5077

Abstract: A method of manufacturing a system on a chip and a system on a chip including a set of pre-designed modules. These modules are place on a semiconductor and connecting by a set of busses formed according to a set of design rules specifying tracks having a minimum size of conductors and a minimum spacing between conductors. The busses are routed in a preferred direction. The busses include minimum size conductors at alternate tracks within a selected metal layer of the semiconductor and minimum size conductors at alternate tracks in a different metal layer. The conductors in the different metal layer are connected to corresponding connectors in the selected metal layer by vias. Shields of conductors not connected to the bus may be included in tracks not including bus conductors.

Abstract translation: 一种制造芯片上的系统的方法和包括一组预先设计的模块的芯片上的系统。 这些模块位于半导体上并通过根据一组设计规则形成的一组总线连接，指定具有导体的最小尺寸和导体之间的最小间距的轨道。 总线沿优选方向路由。 总线包括在半导体的选定金属层内的交替轨道处的最小尺寸导体和在不同金属层中的交替轨道处的最小尺寸导体。 不同金属层中的导体通过通孔连接到所选金属层中的对应连接器。 未连接到总线的导体的屏蔽可以包括在不包括总线导体的轨道中。

公开(公告)号：US20150212152A1

公开(公告)日：2015-07-30

申请号：US14605354

申请日：2015-01-26

Applicant: Texas Instruments Incorporated

Inventor： Khushboo Agarwal ,  Sanjay Krishna H V ,  Raashid Moin Shaikh ,  Srivaths Ravi ,  Wilson Pradeep ,  Rajesh Kumar Tiwari

IPC: G01R31/3177

CPC classification number: G01R31/31721 ,  G01R31/31707 ,  G01R31/31727

Abstract: Methods for testing an application specific integrated circuit (ASIC). A set of representations is created that overlays power density information and clock gate physical locations of a set of clock gates in a critical sub-chip of the ASIC for test mode power analysis. The set of representations are further grouped in the sub-chip into various groups based on overlapping of the set of representations. Then, a set of test control signals is generated corresponding to each of the set of clock gates during at-speed test mode of operation such that each clock gate with overlapping representations receive different test control signals. Further, patterns are generated using a virtual constraint function to selectively enable the set of test control signals such that the set of test control signals are not activated simultaneously.

Abstract translation: 用于测试专用集成电路（ASIC）的方法。 创建一组表示，覆盖用于测试模式功率分析的ASIC的关键子芯片中的一组时钟门的功率密度信息和时钟门物理位置。 基于所述一组表示的重叠，所述表示集合进一步分组成各个组。 然后，在高速测试操作模式期间，对应于该组时钟门限中的每一个产生一组测试控制信号，使得每个具有重叠表示的时钟门接收不同的测试控制信号。 此外，使用虚拟约束函数生成模式以选择性地启用该组测试控制信号，使得该组测试控制信号不被同时激活。

公开(公告)号：US08806413B2

公开(公告)日：2014-08-12

申请号：US14028834

申请日：2013-09-17

Applicant: Texas Instruments Incorporated

Inventor： Raashid Moin Shaikh ,  Vishnuraj Arukat Rajan

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/84

Abstract: A method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select, placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist. The derate value for a predetermined number of circuit path depths below k are identical. The derate values are monotonically decreasing for increasing circuit depths in a range between 1.0 and 1.5. Separate timing model tables with differing identical values can be employed for standard and clock tree cells.

Abstract translation: 一种制造半导体电路的方法是使用每个单元的延迟来寻找预先选择的，放置的和路由的单元组的定时闭合，该延迟是由从具有对应于所述电路路径深度的降额值的定时模型表获得的降额值降低的 网表。 预定数量的电路路径深度低于k的降额值是相同的。 在1.0和1.5之间的范围内增加电路深度时，降额值单调递减。 可以对标准和时钟树单元采用具有不同相同值的单独时序模型表。

公开(公告)号：US20140082248A1

公开(公告)日：2014-03-20

申请号：US14028811

申请日：2013-09-17

Applicant: Texas Instruments Incorporated

Inventor： Raashid Moin Shaikh ,  Vishnuraj Arukat Rajan

IPC: G06F17/50 ,  G06F13/40

CPC classification number: G06F17/5081 ,  G06F13/4027 ,  G06F17/5077

Abstract: A method of manufacturing a system on a chip and a system on a chip including a set of pre-designed modules. These modules are place on a semiconductor and connecting by a set of busses formed according to a set of design rules specifying tracks having a minimum size of conductors and a minimum spacing between conductors. The busses are routed in a preferred direction. The busses include minimum size conductors at alternate tracks within a selected metal layer of the semiconductor and minimum size conductors at alternate tracks in a different metal layer. The conductors in the different metal layer are connected to corresponding connectors in the selected metal layer by vias. Shields of conductors not connected to the bus may be included in tracks not including bus conductors.

Abstract translation: 一种制造芯片上的系统的方法和包括一组预先设计的模块的芯片上的系统。 这些模块位于半导体上并通过根据一组设计规则形成的一组总线连接，指定具有导体的最小尺寸和导体之间的最小间距的轨道。 总线沿优选方向路由。 总线包括在半导体的选定金属层内的交替轨道处的最小尺寸导体和在不同金属层中的交替轨道处的最小尺寸导体。 不同金属层中的导体通过通孔连接到所选金属层中的对应连接器。 未连接到总线的导体的屏蔽可以包括在不包括总线导体的轨道中。