公开(公告)号：US20240213935A1

公开(公告)日：2024-06-27

申请号：US18088091

申请日：2022-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sumit Dubey ,  Rejin Kanjavalappil Raveendranathath ,  Shaik Asif Basha

IPC: H03F3/217 ,  H03F1/32

CPC classification number: H03F3/2173 ,  H03F1/3205 ,  H03F2200/03 ,  H03F2200/351

Abstract: Examples of amplifiers and components thereof are configured to adjust the OFF-pulse widths of a high-duty cycle pulse width modulated (PWM) output signal and the ON-pulse widths of a low-duty cycle PWM output signal. Such control is carried out using high- and low-side (HS and LS) detectors. The HS detector coupled to the control terminal of an HS transistor detects when the gate-to-source voltage (Vgs) of the HS transistor drops below a threshold and outputs an HS detection signal to adjust the OFF-pulse widths of the high-duty cycle PWM output signal. An LS detector coupled to the control terminal of an LS transistor detects when the Vgs of the LS transistor drops below the threshold and outputs a LS detection signal to adjust the ON-pulse widths of the low-duty cycle PWM output signal.

公开(公告)号：US20220094312A1

公开(公告)日：2022-03-24

申请号：US17503405

申请日：2021-10-18

Applicant: Texas Instruments Incorporated

Inventor： Shaik Asif Basha ,  Mohit Chawla ,  Jasjot Singh Chadha

IPC: H03F3/217 ,  H03K4/90

Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.

公开(公告)号：US11923813B2

公开(公告)日：2024-03-05

申请号：US17503405

申请日：2021-10-18

Applicant: Texas Instruments Incorporated

Inventor： Shaik Asif Basha ,  Mohit Chawla ,  Jasjot Singh Chadha

IPC: H03F3/217 ,  H03F3/185 ,  H03F3/38 ,  H03K4/90

CPC classification number: H03F3/2173 ,  H03K4/90 ,  H03F2200/03 ,  H03F2200/351

Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.

公开(公告)号：US11177785B1

公开(公告)日：2021-11-16

申请号：US17024994

申请日：2020-09-18

Applicant: Texas Instruments Incorporated

Inventor： Shaik Asif Basha ,  Mohit Chawla ,  Jasjot Singh Chadha

IPC: H03F3/38 ,  H03F3/185 ,  H03F3/217 ,  H03K4/90

Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.