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公开(公告)号：US20240305321A1
公开(公告)日：2024-09-12
申请号：US18668397
申请日：2024-05-20
发明人： Karthik SUBBURAJ , Pranav SINHA , Mayank Kumar SINGH , Rittu SACHDEV , Karan Singh BHATIA , Shailesh JOSHI , Indu PRATHAPAN
CPC分类号： H04B1/0075 , H04B1/04 , H04B1/1036 , H04B1/69 , H04B2001/0408 , H04B2001/1045 , H04B2001/1063 , H04B2001/6912
摘要： In a radar system, an intermediate frequency amplifier (IFA) is configured with two high-pass filter stages, each having an amplifier and a configurable impedance component. A control signal is activated as the radar system begins to transmit a chirp signal to lower the impedance of the configurable impedance components during an initial portion of the chirp transmission to achieve faster settling of the IFA output signal. After the initial portion, the control signal deactivates while transmission of the chirp continues to increase the impedance of the configurable impedance components to a level sufficient to effectively perform filtering of unwanted signals received by the radar system.
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公开(公告)号：US20240288563A1
公开(公告)日：2024-08-29
申请号：US18654683
申请日：2024-05-03
发明人： Karthik SUBBURAJ , Karthik RAMASUBRAMANIAN , Shailesh JOSHI , Kameswaran VENGATTARAMANE , Indu PRATHAPAN
IPC分类号： G01S13/04 , G01S7/35 , G06F16/22 , G06F16/901 , G06F17/14
CPC分类号： G01S13/04 , G01S7/35 , G06F16/2264 , G06F16/9017 , G06F17/142
摘要： Systems and instruction carrying non-transitory processor-readable mediums are provided to facilitate access of radar data that may be scattered or non-uniformly located within a region of memory for further processing of such radar data. An example system includes counters that increment on different dimensions of the memory region, a lookup table, multipliers, an adder, and a wraparound mechanism to access different sets of non-contiguously stored radar data from a region of memory. The wraparound mechanism performs a wraparound operation when a combined address, generated by the adder based on addresses obtained by the multipliers, is greater than a last valid address in the region. The wraparound operation generates a new combined address that is used to fetch data from the memory. A transform operation is then performed on the fetched data.
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公开(公告)号：US20230017031A1
公开(公告)日：2023-01-19
申请号：US17498342
申请日：2021-10-11
摘要： A non-transitory computer-readable storage device stores machine instructions which, when executed by a processor, cause the processor to determine a chirp period Tc for radar chirps in a radar frame. The chirp period Tc comprises a rising period Trise and a falling period Tfall. The processor determines, for each radar chirp in the radar frame, a corresponding randomized frequency characteristic during Tfall, and causes a radar sensor circuit to generate the radar chirps in the radar frame based on Tc, Trise, Tfall, and the corresponding randomized frequency characteristics. In some implementations, the machine instructions to determine the corresponding randomized frequency characteristic comprise machine instructions to determine a frequency step having a frequency f_step and a period Tstep. At least one of the frequency f_step and the period Tstep is dithered across radar chirps in the radar frame.
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公开(公告)号：US20220366004A1
公开(公告)日：2022-11-17
申请号：US17357919
申请日：2021-06-24
IPC分类号： G06F17/14
摘要： A device includes a comparison circuit and a calculation circuit coupled to the comparison circuit. The comparison circuit is configured to receive a first digital input value (X) and a second digital input value (Y), and provide a first digital output value that indicates one of a first relationship, a second relationship, and a third relationship between X and Y. The calculation circuit is configured to receive X and Y, receive the first digital output value, and provide a second digital output value. The second digital output value is a first linear combination of X and Y responsive to the first digital output value indicating the first relationship, a second linear combination of X and Y responsive to the first digital output value indicating the second relationship, and a third linear combination of X and Y responsive to the first digital output value indicating the third relationship.
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公开(公告)号：US20240094335A1
公开(公告)日：2024-03-21
申请号：US18526250
申请日：2023-12-01
CPC分类号： G01S7/2813 , G01S7/352
摘要： Non-transitory computer-readable mediums and systems are provided in which a portion of each chirp of a series of chirps is held at an offset frequency for a period of time, and in which the offset frequency, the period of time or both is varied or dithered across the chirps of the series of chirps. The portion of a chirp that is held at an offset frequency for a period of time may be a non-active portion of the chirp, during which the chirp is not sampled. In some implementations, the portion of a chirp that is held at an offset frequency for a period of time is during a falling portion of the chirp, which may be at the beginning of the falling portion, or at the end of the falling portion immediately before a rise portion of a succeeding chirp.
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公开(公告)号：US20230216528A1
公开(公告)日：2023-07-06
申请号：US17566047
申请日：2021-12-30
发明人： Karthik SUBBURAJ , Pranav SINHA , Mayank Kumar SINGH , Rittu SACHDEV , Karan Singh BHATIA , Shailesh JOSHI , Indu PRATHAPAN
CPC分类号： H04B1/0075 , H04B1/1036 , H04B1/04 , H04B1/69 , H04B2001/6912 , H04B2001/0408 , H04B2001/1063 , H04B2001/1045
摘要： A device comprises a digital ramp generator, an oscillator, a power amplifier, a low-noise amplifier (LNA), a mixer, and an intermediate frequency amplifier (IFA). The oscillator generates a chirp signal based on an output from the digital ramp generator. The power amplifier receives the chirp signal and outputs an amplified chirp signal to a transmitter antenna. The LNA receives a reflected chirp signal from a receiver antenna. The mixer receives output of the LNA and combines it with the chirp signal from the oscillator. The IFA receives the mixer output signal and includes a configurable high-pass filter, which has a first cutoff frequency during a first portion of the chirp signal and a second cutoff frequency during a second portion of the chirp signal. In some implementations, the first cutoff frequency is chosen based on a frequency of a blocker signal introduced by couplings between the transmitter and receiver antennas.
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公开(公告)号：US20220120884A1
公开(公告)日：2022-04-21
申请号：US17351654
申请日：2021-06-18
发明人： Karthik SUBBURAJ , Karthik RAMASUBRAMANIAN , Shailesh JOSHI , Kameswaran VENGATTARAMANE , Indu PRATHAPAN
IPC分类号： G01S13/04 , G01S7/35 , G06F17/14 , G06F16/22 , G06F16/901
摘要： A system includes a memory configured to store a two-dimensional data structure that includes radar data arranged such that radar data of a first transmitter is separated from radar data of a second transmitter by a Doppler offset in the two-dimensional data structure. The system also includes a data fetch mechanism that includes a lookup table (LUT) applied on either of two dimensions. The lookup table is configured to store a data fetch location in the two-dimensional data structure, where the data fetch location indicates a location from which to fetch a subset of the radar data from the two-dimensional data structure and the data fetch mechanism is configured to fetch the subset of the radar data from the two-dimensional data structure based on the LUT. The system includes a processor configured to perform a fast Fourier transform (FFT) on the fetched subset of the radar data.
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