公开(公告)号：US20150317087A1

公开(公告)日：2015-11-05

申请号：US14270165

申请日：2014-05-05

Applicant: Texas Instruments Incorporated

Inventor： Rakesh Yaraduyathinahalli Channabasappa ,  Shekhar Dinkar Patil ,  Rajeev Suvarna

IPC: G06F3/06

CPC classification number: G06F5/10 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G11C8/16

Abstract: An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.

Abstract translation: 一种装置包括控制器和逻辑电路。 控制器被配置为生成多个单位逻辑值。 每个单位逻辑值具有（i）指示数据分组已经被写入存储器的第一值和（ii）指示已经从存储器读取数据分组的第二值。 逻辑电路被配置为串行堆栈单个位逻辑值。 该装置还可以包括配置为存储单位逻辑值的移位存储器组。 逻辑电路可以被配置为串行堆叠移位存储体中的单位逻辑值。 例如，逻辑电路可以被配置为在不同方向上移位移位存储器组中的单位逻辑值，并且根据一个逻辑值是否具有第一个逻辑值将一个单位逻辑值插入不同端的存储体 或第二个值。

公开(公告)号：US20160035399A1

公开(公告)日：2016-02-04

申请号：US14515326

申请日：2014-10-15

Applicant: Texas Instruments Incorporated

Inventor： Rakesh Channabasappa Yaraduyathinahalli ,  Shekhar Dinkar Patil

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G06F5/10 ,  G06F2205/102 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412

Abstract: The disclosure provides an asynchronous FIFO circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory receives a write clock and a read clock. A FIFO write pointer counter receives a write enable signal and the write clock. The FIFO write pointer counter provides a FIFO write pointer signal to the data memory. A FIFO read pointer counter receives a read enable signal and the read clock. The FIFO read pointer counter provides a FIFO read pointer signal to the data memory. A control circuit receives the write enable signal, the read enable signal, the FIFO write pointer signal, the FIFO read pointer signal, the write clock and the read clock. The control circuit generates a memory full signal when the data memory is full and a memory empty signal when the data memory is empty.

Abstract translation: 本公开提供了一种异步FIFO电路，其包括耦合到写入数据路径和读取数据路径的数据存储器。 数据存储器接收写时钟和读时钟。 FIFO写指针计数器接收写使能信号和写时钟。 FIFO写指针计数器向数据存储器提供FIFO写指针信号。 FIFO读指针计数器接收读使能信号和读时钟。 FIFO读指针计数器向数据存储器提供FIFO读指针信号。 控制电路接收写使能信号，读使能信号，FIFO写指针信号，FIFO读指针信号，写时钟和读时钟。 当数据存储器已满时，控制电路产生存储器满信号，当数据存储器为空时，产生存储器空信号。

公开(公告)号：US10095474B2

公开(公告)日：2018-10-09

申请号：US14270165

申请日：2014-05-05

Applicant: Texas Instruments Incorporated

Inventor： Rakesh Yaraduyathinahalli Channabasappa ,  Shekhar Dinkar Patil ,  Rajeev Suvarna

IPC: G06F3/06 ,  G06F5/10 ,  G11C8/16

Abstract: An apparatus includes a controller and logic circuitry. The controller is configured to generate multiple single-bit logic values. Each single-bit logic value has one of (i) a first value indicating that a data packet has been written into a memory and (ii) a second value indicating that a data packet has been read from the memory. The logic circuitry is configured to serially stack the single-bit logic values. The apparatus could further include a shift memory bank configured to store the single-bit logic values. The logic circuitry can be configured to serially stack the single-bit logic values in the shift memory bank. For example, the logic circuitry can be configured to shift the single-bit logic values in the shift memory bank in different directions and insert one single-bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.

公开(公告)号：US09275704B2

公开(公告)日：2016-03-01

申请号：US14515326

申请日：2014-10-15

Applicant: Texas Instruments Incorporated

Inventor： Rakesh Channabasappa Yaraduyathinahalli ,  Shekhar Dinkar Patil

IPC: G11C8/16 ,  G11C7/22 ,  G11C7/10 ,  G11C11/412

CPC classification number: G11C7/22 ,  G06F5/10 ,  G06F2205/102 ,  G11C7/10 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412

Abstract: The disclosure provides an asynchronous FIFO circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory receives a write clock and a read clock. A FIFO write pointer counter receives a write enable signal and the write clock. The FIFO write pointer counter provides a FIFO write pointer signal to the data memory. A FIFO read pointer counter receives a read enable signal and the read clock. The FIFO read pointer counter provides a FIFO read pointer signal to the data memory. A control circuit receives the write enable signal, the read enable signal, the FIFO write pointer signal, the FIFO read pointer signal, the write clock and the read clock. The control circuit generates a memory full signal when the data memory is full and a memory empty signal when the data memory is empty.

Abstract translation: 本公开提供了一种异步FIFO电路，其包括耦合到写入数据路径和读取数据路径的数据存储器。 数据存储器接收写时钟和读时钟。 FIFO写指针计数器接收写使能信号和写时钟。 FIFO写指针计数器向数据存储器提供FIFO写指针信号。 FIFO读指针计数器接收读使能信号和读时钟。 FIFO读指针计数器向数据存储器提供FIFO读指针信号。 控制电路接收写使能信号，读使能信号，FIFO写指针信号，FIFO读指针信号，写时钟和读时钟。 当数据存储器已满时，控制电路产生存储器满信号，当数据存储器为空时，产生存储器空信号。