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公开(公告)号：US07286441B1
公开(公告)日：2007-10-23
申请号：US11542862
申请日：2006-10-04
IPC分类号： G11C8/00
CPC分类号： G06F13/1689
摘要： A memory system comprises a memory that includes at least one of Synchronous Dynamic Random Access Memory (SDRAM) and Double Data Rate SDRAM (DDR). A memory controller communicates with the memory, generates an SDRAM clock signal, and receives a bi-directional sampling clock signal (DQS). When the memory includes the DDR, the memory generates the DQS. When the memory includes the SDRAM, the DQS is based on the SDRAM clock signal.
摘要翻译： 存储器系统包括包括同步动态随机存取存储器（SDRAM）和双数据速率SDRAM（DDR）中的至少一个的存储器。 存储器控制器与存储器通信，产生SDRAM时钟信号，并接收双向采样时钟信号（DQS）。 当内存包含DDR时，内存会产生DQS。 当存储器包括SDRAM时，DQS基于SDRAM时钟信号。
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公开(公告)号：US07596053B1
公开(公告)日：2009-09-29
申请号：US11542726
申请日：2006-10-04
IPC分类号： G11C11/00
CPC分类号： G06F13/1689
摘要： A circuit for reading data from a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) comprises logic for managing programmable clock signal relationships such that data that is read from the DDR is centered within a DQS signal which is generated from the DDR and then appropriately delayed.
摘要翻译： 用于从缓冲存储器（即同步动态随机存取存储器（“SDRAM”）或双数据速率同步动态随机存取存储器（“DDR”）读取数据的电路包括用于管理可编程时钟信号关系的逻辑， 从DDR中读取的是以DDR产生的DQS信号为中心，然后适当地延迟。
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公开(公告)号：US07120084B2
公开(公告)日：2006-10-10
申请号：US10867113
申请日：2004-06-14
IPC分类号： G11C8/18
CPC分类号： G06F13/1689
摘要： A system and circuit for reading and writing data to a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) is provided. The circuit includes logic for managing programmable clock signal relationships such that data arrives at an optimum time for writing. Data that is to be written at DDR is moved from a first buffer clock to a DDR write clock signal and to a DQS signal that is based on a SDRAM clock signal. Also, plural tap-cells may be used to delay clock signals such that data and clock signals are aligned. An emulated DQS signal in a DDR capture scheme is used for reading from a SDRAM.
摘要翻译： 提供了一种用于将数据读取和写入到同步动态随机存取存储器（“SDRAM”）或双数据速率同步动态随机存取存储器（“DDR”）的缓冲存储器的系统和电路。 该电路包括用于管理可编程时钟信号关系的逻辑，使得数据到达最佳写入时间。 将要写入DDR的数据从第一缓冲时钟移动到DDR写入时钟信号和基于SDRAM时钟信号的DQS信号。 此外，可以使用多个抽头单元来延迟时钟信号，使得数据和时钟信号对齐。 采用DDR采集方案的模拟DQS信号用于从SDRAM读取。
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公开(公告)号：US07535791B1
公开(公告)日：2009-05-19
申请号：US11977169
申请日：2007-10-23
IPC分类号： G11C8/00
CPC分类号： G06F13/1689
摘要： A memory system includes Synchronous Dynamic Random Access Memory (SDRAM) A memory controller communicates with the memory, generates an SDRAM clock signal, that receives a bi-directional sampling clock signal (DQS) that is generated based on the SDRAM clock signal, and reads data from the memory based on the DQS.
摘要翻译： 存储器系统包括同步动态随机存取存储器（SDRAM）。 存储器控制器与存储器通信，产生SDRAM时钟信号，其接收基于SDRAM时钟信号生成的双向采样时钟信号（DQS），并且基于DQS从存储器读取数据。
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公开(公告)号：US07526691B1
公开(公告)日：2009-04-28
申请号：US10686151
申请日：2003-10-15
IPC分类号： G01R31/317 , G01R31/40
CPC分类号： G01R31/318555 , G01R31/318558 , G01R31/318591
摘要： A system and method for dynamically writing to and reading from an internal register space of a chip using a TAP controller without interfering with the normal operation of the chip is provided. Data that is to be written is loaded into a data register in the TAP controller before being written in the internal register space and the write instructions are loaded into an instruction register of the TAP controller. The address of the internal register space from where data is to be read is also loaded to the data register. Data is read and/or written from the internal register space after the TAP controller gets access to the internal register space via arbitration.
摘要翻译： 提供一种用于使用TAP控制器动态写入和读取芯片的内部寄存器空间而不干扰芯片的正常操作的系统和方法。 要写入的数据在被写入内部寄存器空间之前被加载到TAP控制器的数据寄存器中，写入指令被加载到TAP控制器的指令寄存器中。 要从中读取数据的内部寄存器空间的地址也被加载到数据寄存器。 在TAP控制器通过仲裁访问内部寄存器空间之后，从内部寄存器空间读取和/或写入数据。
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公开(公告)号：US07240267B2
公开(公告)日：2007-07-03
申请号：US10983944
申请日：2004-11-08
申请人： Dinesh Jayabharathi
发明人： Dinesh Jayabharathi
IPC分类号： G01R31/28
摘要： Method and system for initiating a built in self test (“BIST”) operation for memory modules is provided. The method includes, determining if a test access port (“TAP”) controller instruction or an internal register control bit are to be used for initiating the BIST operation; sending the internal register control bit to a memory BIST controller for initiating the BIST operation; and setting a status bit in the internal register after the BIST operation is complete. The system includes a storage controller with an internal register for setting a control bit for initiating a BIST operation; a test access port (“TAP”) controller for sending an instruction to a memory BIST controller to initiate a BIST operation; and a multiplexer for selecting between the control bit and the instruction for initiating the BIST operation.
摘要翻译： 提供了用于启动内存模块的内置自检（“BIST”）操作的方法和系统。 该方法包括：确定测试访问端口（“TAP”）控制器指令或内部寄存器控制位是否用于启动BIST操作; 将内部寄存器控制位发送到存储器BIST控制器以启动BIST操作; 并在BIST操作完成后，在内部寄存器中设置一个状态位。 该系统包括具有用于设置用于启动BIST操作的控制位的内部寄存器的存储控制器; 测试访问端口（“TAP”）控制器，用于向存储器BIST控制器发送指令以启动BIST操作; 以及用于在控制位和用于启动BIST操作的指令之间进行选择的多路复用器。
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公开(公告)号：US20050276151A1
公开(公告)日：2005-12-15
申请号：US10867113
申请日：2004-06-14
CPC分类号： G06F13/1689
摘要： A system and circuit for reading and writing data to a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) is provided. The circuit includes logic for managing programmable clock signal relationships such that data arrives at an optimum time for writing. Data that is to be written at DDR is moved from a first buffer clock to a DDR write clock signal and to a DQS signal that is based on a SDRAM clock signal. Also, plural tap-cells may be used to delay clock signals such that data and clock signals are aligned. An emulated DQS signal in a DDR capture scheme is used for reading from a SDRAM.
摘要翻译： 提供了一种用于将数据读取和写入到同步动态随机存取存储器（“SDRAM”）或双数据速率同步动态随机存取存储器（“DDR”）的缓冲存储器的系统和电路。 该电路包括用于管理可编程时钟信号关系的逻辑，使得数据到达最佳写入时间。 将要写入DDR的数据从第一缓冲时钟移动到DDR写入时钟信号和基于SDRAM时钟信号的DQS信号。 此外，可以使用多个抽头单元来延迟时钟信号，使得数据和时钟信号对齐。 采用DDR采集方案的模拟DQS信号用于从SDRAM读取。
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公开(公告)号：US20060117235A1
公开(公告)日：2006-06-01
申请号：US10983944
申请日：2004-11-08
申请人： Dinesh Jayabharathi
发明人： Dinesh Jayabharathi
IPC分类号： G01R31/28
摘要： Method and system for initiating a built in self test (“BIST”) operation for memory modules is provided. The method includes, determining if a test access port (“TAP”) controller instruction or an internal register control bit are to be used for initiating the BIST operation; sending the internal register control bit to a memory BIST controller for initiating the BIST operation; and setting a status bit in the internal register after the BIST operation is complete. The system includes a storage controller with an internal register for setting a control bit for initiating a BIST operation; a test access port (“TAP”) controller for sending an instruction to a memory BIST controller to initiate a BIST operation; and a multiplexer for selecting between the control bit and the instruction for initiating the BIST operation.
摘要翻译： 提供了用于启动内存模块的内置自检（“BIST”）操作的方法和系统。 该方法包括：确定测试访问端口（“TAP”）控制器指令或内部寄存器控制位是否用于启动BIST操作; 将内部寄存器控制位发送到存储器BIST控制器以启动BIST操作; 并在BIST操作完成后，在内部寄存器中设置一个状态位。 该系统包括具有用于设置用于启动BIST操作的控制位的内部寄存器的存储控制器; 测试访问端口（“TAP”）控制器，用于向存储器BIST控制器发送指令以启动BIST操作; 以及用于在控制位和用于启动BIST操作的指令之间进行选择的多路复用器。
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公开(公告)号：US08015448B2
公开(公告)日：2011-09-06
申请号：US11820226
申请日：2007-06-19
申请人： Dinesh Jayabharathi
发明人： Dinesh Jayabharathi
IPC分类号： G06F11/00
摘要： A storage controller including a first controller. The first controller includes a memory module, a test access port controller, the test access port controller configured to control a built in self-test operation on the memory module, and a register configured to store a first instruction. In response to the storage controller detecting a test access port interface being accessible to the storage controller, the test access port controller is configured to control the built in self-test operation on the memory module of the first controller by having either (i) a second instruction sent from the test access port controller to the first controller or (ii) the first instruction sent from the register to the first controller. The first controller is configured to perform the built in self-test operation on the memory module in response to having received the first instruction or having received the second instruction.
摘要翻译： 一种存储控制器，包括第一控制器。 第一控制器包括存储器模块，测试访问端口控制器，被配置为控制对存储器模块的内置自检操作的测试访问端口控制器以及被配置为存储第一指令的寄存器。 响应于所述存储控制器检测到所述存储控制器可访问的测试访问端口接口，所述测试访问端口控制器被配置为通过以下操作来控制对所述第一控制器的所述存储器模块的内置自检操作：（i） 从测试访问端口控制器发送到第一控制器的第二指令，或者（ii）从寄存器发送到第一控制器的第一指令。 第一控制器被配置为响应于已经接收到第一指令或已经接收到第二指令而对存储器模块执行内置自检操作。
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公开(公告)号：US20070250740A1
公开(公告)日：2007-10-25
申请号：US11820226
申请日：2007-06-19
申请人： Dinesh Jayabharathi
发明人： Dinesh Jayabharathi
IPC分类号： G06F11/27
摘要： A built in self test (BIST) system for a storage controller comprises a processor, a test access port (TAP) controller that communicates with a TAP interface that is external to the storage controller, and a BIST controller that selectively performs a BIST based on information received from each of the processor and the TAP controller.
摘要翻译： 用于存储控制器的内置自检（BIST）系统包括处理器，与存储控制器外部的TAP接口进行通信的测试访问端口（TAP）控制器，以及基于BIST控制器选择性地执行BIST的BIST控制器 从每个处理器和TAP控制器接收的信息。
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