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1.发明申请SYSTEM AND METHOD FOR SETTING ACCESS AND MODIFICATION FOR SYNCHRONOUS SERIAL INTERFACE NAND 有权用于同步串行接口NAND的设置访问和修改的系统和方法公开(公告)号：US20090103362A1
公开(公告)日：2009-04-23
申请号：US11873826
申请日：2007-10-17
申请人： Theodore T. Pekny , Victor Y. Tsai
发明人： Theodore T. Pekny , Victor Y. Tsai
CPC分类号： G11C7/1021 , G06F3/0619 , G06F3/0629 , G06F3/0679 , G06F12/145 , G06F13/1694 , G06F2212/1052 , G11C7/1072
摘要： The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.
摘要翻译： 本发明包括使用从主机到NAND闪存器件的串行外设接口（SPI）通信来修改NAND闪存器件的设置的系统和方法。 一个实施例通常包括将启用信号发送到第一存储器电路输入，向第二存储器电路输入发送时钟信号，向第三存储器电路输入发送与时钟信号同步的命令信号，发送与第一存储器电路输入同步的存储器寄存器地址信号 时钟信号输入到第三存储器电路，并将与时钟信号同步的设置信号发送到第三存储器电路输入。
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公开(公告)号：US20130124946A1
公开(公告)日：2013-05-16
申请号：US13735789
申请日：2013-01-07
CPC分类号： G06F13/4291 , G06F3/0619 , G06F3/0629 , G06F3/0679 , G06F11/1064 , G06F11/1068 , G11C7/1006 , G11C16/26 , G11C2207/104 , G11C2207/2245 , G11C2216/30
摘要： A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.
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3.发明申请SYSTEM AND METHOD FOR SETTING ACCESS AND MODIFICATION FOR SYNCHRONOUS SERIAL INTERFACE NAND 有权用于同步串行接口NAND的设置访问和修改的系统和方法公开(公告)号：US20120124279A1
公开(公告)日：2012-05-17
申请号：US13357533
申请日：2012-01-24
申请人： Theodore T. Pekny , Victor Y. Tsai
发明人： Theodore T. Pekny , Victor Y. Tsai
IPC分类号： G06F12/02
CPC分类号： G11C7/1021 , G06F3/0619 , G06F3/0629 , G06F3/0679 , G06F12/145 , G06F13/1694 , G06F2212/1052 , G11C7/1072
摘要： The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.
摘要翻译： 本发明包括使用从主机到NAND闪存器件的串行外设接口（SPI）通信来修改NAND闪存器件的设置的系统和方法。 一个实施例通常包括将启用信号发送到第一存储器电路输入，向第二存储器电路输入发送时钟信号，向第三存储器电路输入发送与时钟信号同步的命令信号，发送与第一存储器电路输入同步的存储器寄存器地址信号 时钟信号输入到第三存储器电路，并将与时钟信号同步的设置信号发送到第三存储器电路输入。
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4.发明授权公开(公告)号：US08103936B2
公开(公告)日：2012-01-24
申请号：US11873833
申请日：2007-10-17
IPC分类号： G11C29/00
CPC分类号： G06F13/4291 , G06F3/0619 , G06F3/0629 , G06F3/0679 , G06F11/1064 , G06F11/1068 , G11C7/1006 , G11C16/26 , G11C2207/104 , G11C2207/2245 , G11C2216/30
摘要： A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.
摘要翻译： 公开了一种用于操作NAND存储器件的方法和系统。 通过从主机向NAND存储器件发送串行外设接口信号来操作NAND存储器件，由此将信号传送到NAND存储器件中的NAND存储器，而不将信号修改为标准NAND存储器格式。 类似地，公开了用于从NAND存储器件接收信号而不将来自标准NAND格式的信号修改成串行格式的方法和系统。 该系统还包括错误检测和校正技术来检测和校正存储在NAND存储器件中的数据中的错误。
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5.发明授权System and method for setting access and modification for synchronous serial interface NAND 有权用于设置同步串行接口NAND的访问和修改的系统和方法公开(公告)号：US08102710B2
公开(公告)日：2012-01-24
申请号：US11873826
申请日：2007-10-17
申请人： Theodore T. Pekny , Victor Y. Tsai
发明人： Theodore T. Pekny , Victor Y. Tsai
CPC分类号： G11C7/1021 , G06F3/0619 , G06F3/0629 , G06F3/0679 , G06F12/145 , G06F13/1694 , G06F2212/1052 , G11C7/1072
摘要： The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a master to the NAND flash memory device. One embodiment generally includes sending an enable signal to a first memory circuit input, sending a clock signal to a second memory circuit input, sending a command signal synchronized to the clock signal to a third memory circuit input, sending a memory register address signal synchronized to the clock signal to the third memory circuit input, and sending a setting signal synchronized to the clock signal to the third memory circuit input.
摘要翻译： 本发明包括使用从主机到NAND闪存器件的串行外设接口（SPI）通信来修改NAND闪存器件的设置的系统和方法。 一个实施例通常包括将启用信号发送到第一存储器电路输入，向第二存储器电路输入发送时钟信号，向第三存储器电路输入发送与时钟信号同步的命令信号，发送与第一存储器电路输入同步的存储器寄存器地址信号 时钟信号输入到第三存储器电路，并将与时钟信号同步的设置信号发送到第三存储器电路输入。
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6.发明授权公开(公告)号：US08694860B2
公开(公告)日：2014-04-08
申请号：US13735789
申请日：2013-01-07
IPC分类号： G11C29/00
CPC分类号： G06F13/4291 , G06F3/0619 , G06F3/0629 , G06F3/0679 , G06F11/1064 , G06F11/1068 , G11C7/1006 , G11C16/26 , G11C2207/104 , G11C2207/2245 , G11C2216/30
摘要： A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.
摘要翻译： 公开了一种用于操作NAND存储器件的方法和系统。 通过从主机向NAND存储器件发送串行外设接口信号来操作NAND存储器件，由此将信号传送到NAND存储器件中的NAND存储器，而不将信号修改为标准NAND存储器格式。 类似地，公开了用于从NAND存储器件接收信号而不将来自标准NAND格式的信号修改成串行格式的方法和系统。 该系统还包括错误检测和校正技术来检测和校正存储在NAND存储器件中的数据中的错误。
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7.发明授权Method for operating a NAND flash memory device in multiple operational modes 有权用于以多种操作模式操作NAND闪速存储器件的方法公开(公告)号：US08687422B2
公开(公告)日：2014-04-01
申请号：US13357533
申请日：2012-01-24
申请人： Theodore T. Pekny , Victor Y. Tsai
发明人： Theodore T. Pekny , Victor Y. Tsai
IPC分类号： G11C11/34
CPC分类号： G11C7/1021 , G06F3/0619 , G06F3/0629 , G06F3/0679 , G06F12/145 , G06F13/1694 , G06F2212/1052 , G11C7/1072
摘要： A method and device are provided for operating in a special mode using a special mode enable register. In one example, a memory device includes registers in volatile memory and a memory array. At least one of the registers may include a special mode bit that controls a special mode of operation of the memory device.
摘要翻译： 提供了一种使用特殊模式使能寄存器在特殊模式下运行的方法和装置。 在一个示例中，存储器件包括易失性存储器中的寄存器和存储器阵列。 寄存器中的至少一个可以包括控制存储器件的特殊工作模式的特殊模式位。
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8.发明授权公开(公告)号：US08352833B2
公开(公告)日：2013-01-08
申请号：US13357536
申请日：2012-01-24
IPC分类号： G11C29/00
CPC分类号： G06F13/4291 , G06F3/0619 , G06F3/0629 , G06F3/0679 , G06F11/1064 , G06F11/1068 , G11C7/1006 , G11C16/26 , G11C2207/104 , G11C2207/2245 , G11C2216/30
摘要： A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.
摘要翻译： 公开了一种用于操作NAND存储器件的方法和系统。 通过从主机向NAND存储器件发送串行外设接口信号来操作NAND存储器件，由此将信号传送到NAND存储器件中的NAND存储器，而不将信号修改为标准NAND存储器格式。 类似地，公开了用于从NAND存储器件接收信号而不将来自标准NAND格式的信号修改成串行格式的方法和系统。 该系统还包括错误检测和校正技术来检测和校正存储在NAND存储器件中的数据中的错误。
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9.发明申请公开(公告)号：US20120124446A1
公开(公告)日：2012-05-17
申请号：US13357536
申请日：2012-01-24
CPC分类号： G06F13/4291 , G06F3/0619 , G06F3/0629 , G06F3/0679 , G06F11/1064 , G06F11/1068 , G11C7/1006 , G11C16/26 , G11C2207/104 , G11C2207/2245 , G11C2216/30
摘要： A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.
摘要翻译： 公开了一种用于操作NAND存储器件的方法和系统。 通过从主机向NAND存储器件发送串行外设接口信号来操作NAND存储器件，由此将信号传送到NAND存储器件中的NAND存储器，而不将信号修改为标准NAND存储器格式。 类似地，公开了用于从NAND存储器件接收信号而不将来自标准NAND格式的信号修改成串行格式的方法和系统。 该系统还包括错误检测和校正技术来检测和校正存储在NAND存储器件中的数据中的错误。
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公开(公告)号：US08543802B2
公开(公告)日：2013-09-24
申请号：US13559162
申请日：2012-07-26
CPC分类号： G06F9/4411 , G06F9/4401
摘要： The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.
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