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    Current driver configuration for MRAM
    2.
    发明授权
    Current driver configuration for MRAM 有权
    MRAM的当前驱动程序配置

    公开(公告)号：US06483768B2

    公开(公告)日：2002-11-19

    申请号：US09898221

    申请日：2001-07-03

    申请人： Thomas Böhm ,  Dietmar Gogl ,  Gerhard Müller ,  Thomas Röhr

    发明人： Thomas Böhm ,  Dietmar Gogl ,  Gerhard Müller ,  Thomas Röhr

    IPC分类号： G11C800

    CPC分类号： G11C11/16 ,  G11C7/12

    摘要： A current driver configuration for MRAMs includes word-line drivers and bit-line drivers at respective first ends of word lines and bit lines. The word line drivers and the bit line drivers each include a series circuit formed by an n-channel field-effect transistor and a current source. Further series circuits are provided at the respective second ends of the word lines and the bit lines. Each of the further series circuits includes a second n-channel field-effect transistor and a voltage source.

    摘要翻译： MRAM的当前驱动器配置包括在字线和位线的相应第一端处的字线驱动器和位线驱动器。 字线驱动器和位线驱动器各自包括由n沟道场效应晶体管和电流源形成的串联电路。 在字线和位线的各自的第二端设置有更多的串联电路。 每个其它串联电路包括第二n沟道场效应晶体管和电压源。

    CMOS voltage divider
    3.
    发明授权
    CMOS voltage divider 有权
    CMOS分压器

    公开(公告)号：US06429731B2

    公开(公告)日：2002-08-06

    申请号：US09816934

    申请日：2001-03-23

    申请人： Thomas Böhm ,  Robert Esterl ,  Stefan Lammers ,  Zoltan Manyoki

    发明人： Thomas Böhm ,  Robert Esterl ,  Stefan Lammers ,  Zoltan Manyoki

    IPC分类号： G05F1595

    CPC分类号： G05F3/242

    摘要： A CMOS voltage divider having a first chain containing series-connected MOS transistors of a first conductivity type is described. Each of the MOS transistors have identical geometrical dimensions and, at the same time, each have identical gate-source voltages. The MOS transistors operate in the linear range of their characteristic curve and between opposite ends of the first chain an input voltage to be divided is present and at whose source terminals the voltage fractions can in each case be picked off. Provision is made of a second chain containing series-connected MOS transistors, complementary to the first MOS transistors. The second chain has the same number of transistors as the first MOS transistors and with the same geometrical dimension in each case. The MOS transistors of the first chain are connected to the MOS transistors of the second chain in such a way that each MOS transistor chain generates the gate-source bias voltage for the respective other MOS transistor chain.

    摘要翻译： 描述了具有包含第一导电类型的串联MOS晶体管的第一链的CMOS分压器。 每个MOS晶体管具有相同的几何尺寸，并且同时具有相同的栅源电压。 MOS晶体管在其特性曲线的线性范围内工作，并且在第一链的相对端之间存在待分割的输入电压，并且在每个情况下，其源极端子的电压分数可以被拾取。 提供了包含与第一MOS晶体管互补的串联MOS晶体管的第二链。 第二链具有与第一MOS晶体管相同数量的晶体管，并且在每种情况下具有相同的几何尺寸。 第一链的MOS晶体管以这样的方式连接到第二链的MOS晶体管，使得每个MOS晶体管链为相应的另一个MOS晶体管链产生栅极 - 源极偏置电压。

    Semiconductor memory device having a plurality of memory areas with memory elements
    5.
    发明授权
    Semiconductor memory device having a plurality of memory areas with memory elements 有权
    具有多个具有存储元件的存储区域的半导体存储器件

    公开(公告)号：US07158405B2

    公开(公告)日：2007-01-02

    申请号：US10190812

    申请日：2002-07-08

    申请人： Thomas Böhm ,  Stefan Lammers ,  Thomas Röhr

    发明人： Thomas Böhm ,  Stefan Lammers ,  Thomas Röhr

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16 ,  G11C8/12

    摘要： A semiconductor memory device has a particularly space-saving configuration of the memory areas and, in particular, of the selection devices assigned to the memory areas. During operation, each selection device can be assigned in a controllable manner to a plurality of memory areas such that selectively each of the selection devices can carry out an addressing and selection in one of the assigned memory areas.

    摘要翻译： 半导体存储器件具有特别节省空间的存储区域配置，特别是分配给存储区域的选择设备。 在操作期间，可以以可控的方式将每个选择装置分配给多个存储区域，使得选择性地每个选择装置可以在分配的存储区域之一中执行寻址和选择。

    Integrated semiconductor memory with redundant units for memory cells
    7.
    发明授权
    Integrated semiconductor memory with redundant units for memory cells 有权
    具有用于存储器单元的冗余单元的集成半导体存储器

    公开(公告)号：US06353562B2

    公开(公告)日：2002-03-05

    申请号：US09780326

    申请日：2001-02-09

    申请人： Thomas Böhm ,  Heinz Hönigschmid ,  Stefan Lammers ,  Zoltan Manyoki

    发明人： Thomas Böhm ,  Heinz Hönigschmid ,  Stefan Lammers ,  Zoltan Manyoki

    IPC分类号： G11C700

    CPC分类号： G11C29/24 ,  G11C29/787

    摘要： An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

    摘要翻译： 集成半导体存储器具有被组合以形成可寻址的正常单元并且形成至少一个用于替换正常单元之一的冗余单元的存储单元。 此外，半导体存储器具有可以应用地址的地址总线，以及连接到地址总线的冗余电路。 冗余电路用于选择冗余单元。 处理单元的输入连接到地址总线的连接，也连接到用于测试信号的连接，并且处理单元的输出连接到冗余电路的输入。 在冗余电路中编写修复信息之前，可以对冗余单元进行测试。 所需的电路复杂度相对较低。

    MRAM configuration
    8.
    发明授权
    MRAM configuration 有权
    MRAM配置

    公开(公告)号：US06473335B2

    公开(公告)日：2002-10-29

    申请号：US09898222

    申请日：2001-07-03

    申请人： Thomas Böhm ,  Helmut Kandolf ,  Stefan Lammers

    发明人： Thomas Böhm ,  Helmut Kandolf ,  Stefan Lammers

    IPC分类号： G11C1100

    CPC分类号： G11C11/16

    摘要： A magneto-resistive random access memory (MRAM) configuration is described in which line driver circuits are respectively assigned via connecting nodes to two memory cell arrays, with the result that the area for the driver circuits can practically be halved. Therefore a space-saving architecture and a more efficient MRAM configuration is obtained.

    摘要翻译： 描述了一种磁阻随机存取存储器（MRAM）配置，其中线路驱动器电路分别经由连接节点分配给两个存储单元阵列，结果是驱动器电路的面积实际上可以减半。 因此，获得节省空间的架构和更有效的MRAM配置。