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    Integrated circuit having a decoder
    3.
    发明授权
    Integrated circuit having a decoder 有权
    具有解码器的集成电路

    公开(公告)号：US06255855B1

    公开(公告)日：2001-07-03

    申请号：US09470310

    申请日：1999-12-22

    申请人： Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Thomas Röhr ,  Thomas Böhm

    发明人： Heinz Hönigschmid ,  Georg Braun ,  Zoltan Manyoki ,  Thomas Röhr ,  Thomas Böhm

    IPC分类号： H03K19084

    CPC分类号： G11C8/00 ,  G11C8/10 ,  H03K19/084 ,  H03K19/094 ,  H03K19/23 ,  H03M5/16

    摘要： An integrated circuit includes a decoder having an output terminal and five input terminals. The decoder has three operating states including a first operating state for generating a first potential at the output terminal, a second operating state for generating a second potential at the output terminal, and a third operating state for generating a third potential at the output terminal. The second potential lies between the first potential and the third potential.

    摘要翻译： 集成电路包括具有输出端和五个输入端的解码器。 解码器具有三个操作状态，包括用于在输出端产生第一电位的第一操作状态，用于在输出端产生第二电位的第二操作状态和用于在输出端产生第三电位的第三操作状态。 第二个潜力位于第一个潜力和第三个潜力之间。

    Integrated memory
    6.
    发明授权
    Integrated memory 有权
    集成内存

    公开(公告)号：US06442100B2

    公开(公告)日：2002-08-27

    申请号：US09904358

    申请日：2001-07-12

    申请人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Röhr

    发明人： Thomas Böhm ,  Georg Braun ,  Heinz Hönigschmid ,  Zoltan Manyoki ,  Thomas Röhr

    IPC分类号： G11C800

    CPC分类号： G11C7/06 ,  G11C7/1048 ,  G11C11/22

    摘要： The integrated memory has m>1 bit lines that are connected to an input of a read-write amplifier via a switching element. Only one switching element is conductively connected for each read or write access. The memory is provided with a switching unit that influences read or write access occurring by way of the read-write amplifier and bit lines. The circuit unit is provided with an activation input. A column-end decoder has a first decoder stage and m second decoder stages. The outputs of the second decoder stages are connected to a control input for each of the switching elements. The output of the first decoder stage is connected to the activation input of the switching unit.

    摘要翻译： 集成存储器具有通过开关元件连接到读写放大器的输入的m≥1位线。 每个读或写访问只有一个开关元件被导电连接。 存储器设置有影响通过读写放大器和位线发生的读取或写入访问的切换单元。 电路单元具有激活输入。 列端解码器具有第一解码器级和m个第二解码器级。 第二解码器级的输出端连接到每个开关元件的控制输入端。 第一解码器级的输出连接到开关单元的启动输入。

    Integrated semiconductor memory with redundant units for memory cells
    9.
    发明授权
    Integrated semiconductor memory with redundant units for memory cells 有权
    具有用于存储器单元的冗余单元的集成半导体存储器

    公开(公告)号：US06353562B2

    公开(公告)日：2002-03-05

    申请号：US09780326

    申请日：2001-02-09

    申请人： Thomas Böhm ,  Heinz Hönigschmid ,  Stefan Lammers ,  Zoltan Manyoki

    发明人： Thomas Böhm ,  Heinz Hönigschmid ,  Stefan Lammers ,  Zoltan Manyoki

    IPC分类号： G11C700

    CPC分类号： G11C29/24 ,  G11C29/787

    摘要： An integrated semiconductor memory has memory cells that are combined to form addressable normal units and to form at least one redundant unit for replacing one of the normal units. In addition, the semiconductor memory has an address bus to which an address can be applied, and a redundancy circuit that is connected to the address bus. The redundancy circuit is used to select the redundant unit. An input of a processing unit is connected to a connection of the address bus and also to a connection for a test signal, and the output of the processing unit is connected to an input of the redundancy circuit. The redundant unit can be tested before the repair information is programmed in the redundancy circuit. The circuit complexity required for this is comparatively low.

    摘要翻译： 集成半导体存储器具有被组合以形成可寻址的正常单元并且形成至少一个用于替换正常单元之一的冗余单元的存储单元。 此外，半导体存储器具有可以应用地址的地址总线，以及连接到地址总线的冗余电路。 冗余电路用于选择冗余单元。 处理单元的输入连接到地址总线的连接，也连接到用于测试信号的连接，并且处理单元的输出连接到冗余电路的输入。 在冗余电路中编写修复信息之前，可以对冗余单元进行测试。 所需的电路复杂度相对较低。

    Integrated memory having sense amplifiers disposed on opposite sides of a cell array
    10.
    发明授权
    Integrated memory having sense amplifiers disposed on opposite sides of a cell array 失效
    具有设置在单元阵列的相对侧上的读出放大器的集成存储器

    公开(公告)号：US06259641B1

    公开(公告)日：2001-07-10

    申请号：US09560545

    申请日：2000-04-28

    申请人： Zoltan Manyoki ,  Thomas Röhr ,  Thomas Böhm

    发明人： Zoltan Manyoki ,  Thomas Röhr ,  Thomas Böhm

    IPC分类号： G11C700

    CPC分类号： G11C11/22 ,  G11C7/06 ,  G11C7/1042

    摘要： An integrated memory includes a cell array having memory cells disposed at points of intersection of first bit lines and second bit lines with word lines in the cell array. When one of the memory cells is addressed, the memory content is not affected if respective bit lines associated with each of the memory cells are at a standby potential. Sense amplifiers for amplifying data read from the memory cells onto the bit lines are included, each associated with respective first and second bit lines and disposed on opposite sides of the cell array. Also provided are first switching elements, through which each bit line is connected to the associated sense amplifier, and second switching elements, through which each bit line is connected, on that side of its first switching element which is remote from the associated sense amplifier, to a standby potential. Column selection lines are each connected to the control connections of the first and second switching elements in at least one of the first and one of the second bit lines. Each bit line is connected to the standby potential through third switching elements. A first control line is connected to all the third switching elements in the first bit lines, and a second control line is connected to all the third switching elements in the second bit lines.

    摘要翻译： 集成存储器包括具有存储单元阵列的单元阵列，该存储单元设置在第一位线和第二位线的交点处与单元阵列中的字线。 当存储器单元之一被寻址时，如果与每个存储器单元相关联的各个位线处于待机电位，则存储器内容不受影响。 包括用于将从存储器单元读取的数据放大到位线的读出放大器，每个与相应的第一和第二位线相关联并且设置在单元阵列的相对侧上。 还提供了第一开关元件，每个位线通过该开关元件连接到相关联的读出放大器，以及在其第一开关元件的远离相关读出放大器的该侧上连接每个位线的第二开关元件， 到备用电位。 列选择线各自连接到第一和第二位线中的至少一个中的第一和第二开关元件的控制连接。 每个位线通过第三个开关元件连接到待机电位。 第一控制线连接到第一位线中的所有第三开关元件，第二控制线连接到第二位线中的所有第三开关元件。