公开(公告)号：US20050039153A1

公开(公告)日：2005-02-17

申请号：US10946552

申请日：2004-09-21

申请人： Thomas Bednar ,  Paul Dunn ,  Scott Gould ,  Jeannie Panner ,  Paul Zuchowski

发明人： Thomas Bednar ,  Paul Dunn ,  Scott Gould ,  Jeannie Panner ,  Paul Zuchowski

IPC分类号： G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC分类号： G06F17/5068 ,  Y10S707/99931

摘要： Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

摘要翻译： 公开了宏观设计技术，以便于跨宏观的后续布线。 重新布置宏中的空白区域以适应布线。 重新布置可以采取将空白区域的物理重新布置成从宏的一侧延伸到另一侧的路由轨道的形式; 使用例如宏功率总线和/或宏布线进行屏蔽; 路由功率总线到重新排列的空格; 和/或插入具有可接线的引脚的有源电路。 在优选实施例中，在后续阶段的设计期间，将有源电路放置在重排的宏空白中。 空白的重新排列有助于宏观上的布线，使得可以保持后续级布线的压摆率和路径延迟要求，而不会过度缓冲或重新布线。

公开(公告)号：US20070047343A1

公开(公告)日：2007-03-01

申请号：US11552166

申请日：2006-10-24

申请人： Janice Adams ,  Frank Distler ,  Mark Ollive ,  Michael Ouellette ,  Jeannie Panner

发明人： Janice Adams ,  Frank Distler ,  Mark Ollive ,  Michael Ouellette ,  Jeannie Panner

IPC分类号： G11C29/00

CPC分类号： G11C29/802 ,  H03K19/1735

摘要： A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.

摘要翻译： 一种用于修复半导体芯片中的有缺陷的存储器的方法和系统。 该芯片具有存储器位置，冗余存储器和用于有序保险丝的中心位置。 有序保险丝以压缩格式识别存储器位置的缺陷部分。 有缺陷的部分可由冗余存储器的部分替换。 有序保险丝具有相关联的熔丝位模式，其顺序地表示压缩格式的缺陷部分。 方法和系统确定存储器位置连接在一起的顺序; 根据存储器位置连接在一起的顺序，通过存储器位置设计锁存器的移位寄存器; 并且将每个锁存器与从其导出熔丝位模式的未压缩位模式的对应位相关联。 未压缩比特模式包括一个比特序列，表示未压缩格式的缺陷部分。