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公开(公告)号：US4298007A
公开(公告)日：1981-11-03
申请号：US170948
申请日：1980-07-21
CPC分类号： A61N1/368
摘要： An electrical pacer device which responds to cardiac demand so as to alter the cardiac output in a fashion to satisfy that demand. Changes in the fundamental period of the atrial electrical cycle are detected and averaged over a predetermined time interval and the resulting control signal is used to raise and lower the ventricular heart rate to increase and decrease the aforesaid cardiac output. At the same time, means are provided for continuously driving the ventricular rate toward a predetermined lower rate (the at rest rate) on a time cycle which is significantly longer than the above-mentioned predetermined time interval.
摘要翻译： 一种响应于心脏需求以便以满足该需求的方式改变心输出量的电子起搏装置。 在预定时间间隔内检测和平均心房电循环的基本周期的变化，并且使用所得到的控制信号来提高和降低心室心率以增加和减少上述心输出量。 同时，提供了用于在明显长于上述预定时间间隔的时间周期上将心室率持续地驱动到预定的较低速率（静止时）的装置。
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公开(公告)号：US4139886A
公开(公告)日：1979-02-13
申请号：US846290
申请日：1977-10-28
申请人： Philip E. White , Robert C. Rust
发明人： Philip E. White , Robert C. Rust
CPC分类号： G11C29/86 , G11C19/0875
摘要： A logic system is disclosed for using a memory device of the serial read type having redundant elements in excess of the nominal memory size and consists of a Programmable Read Only Memory having a defect map programmed into it with respect to the associated memory device, a shift register of a predetermined length equivalent to the maximum number of allowable defects, a multiplexer associated with the shift register, a position counter for controlling the multiplexer and, finally, appropriate logic to control the system. This system is disclosed in connection with a bubble memory system of the field access major loop -- minor loop type having extra minor loops. As defects are encountered in writing, data is shifted through the shift register while the multiplexer is incremented to the proper output position of the shift register based on the number of encountered defects. As data is read, an analogous reverse to writing operation is performed with the multiplexer being decremented. In either writing or reading, the multiplexer will never be shifted more than one position for each data bit.
摘要翻译： 公开了一种逻辑系统，用于使用具有超过标称存储器大小的冗余元件的串行读取类型的存储器件，并且由可编程只读存储器组成，该可编程只读存储器具有相对于相关联的存储器件编程的缺陷映射表， 与等于最大可允许缺陷数量的预定长度的寄存器，与移位寄存器相关联的复用器，用于控制多路复用器的位置计数器，以及最后控制系统的适当逻辑。 该系统结合具有额外次要循环的现场访问主循环 - 小循环类型的气泡存储器系统而公开。 由于在写入时遇到缺陷，数据通过移位寄存器移位，同时多路复用器根据遇到的缺陷数增加到移位寄存器的正确输出位置。 当数据被读取时，与多路复用器递减地执行与写入操作相反的类似操作。 在写入或读取中，多路复用器将不会为每个数据位移位多于一个位置。
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