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公开(公告)号：US07165120B1
公开(公告)日：2007-01-16
申请号：US09689218
申请日：2000-10-11
申请人： Thomas E. Giles , Leo Hejza , Raghvendra Singh
发明人： Thomas E. Giles , Leo Hejza , Raghvendra Singh
IPC分类号： G06F15/16 , G06F15/173 , H05K5/00
CPC分类号： G06F13/4022 , H04L67/1002 , H04L67/1008 , H04L67/1034 , H04L69/12 , H04L69/40
摘要： According to one aspect of the invention, a method and apparatus for a server node is disclosed. This server node consists of one or more processors. The processors are configured to perform server functions as well as switch and router functions including load balancing and fail-over. The server nodes also have a plurality of ports. These ports allow the server nodes to be connected combined to form blocks and networks as well as to provide connection to external networks. When a server node receives a request, it determines whether it can handle the request. If possible, the server node handles the request. If the server node cannot handle the request, it routes the request to a second, neighboring server node.
摘要翻译： 根据本发明的一个方面，公开了一种用于服务器节点的方法和装置。 该服务器节点由一个或多个处理器组成。 处理器配置为执行服务器功能以及交换机和路由器功能，包括负载平衡和故障切换。 服务器节点还具有多个端口。 这些端口允许将服务器节点连接组合以形成块和网络，并提供到外部网络的连接。 当服务器节点接收到请求时，它确定是否可以处理该请求。 如果可能，服务器节点处理该请求。 如果服务器节点无法处理请求，则将请求路由到第二个相邻的服务器节点。
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公开(公告)号：US06915395B1
公开(公告)日：2005-07-05
申请号：US09564202
申请日：2000-05-03
申请人： Raghvendra Singh
发明人： Raghvendra Singh
CPC分类号： G06F9/3834 , G06F9/3851 , G06F12/0842
摘要： A present invention provides a system and method for avoiding memory hazards in a multi-threaded CPU which shares an L-1 data cache. The system includes a CPU and an AACAM. The AACAM is capable of copying memory addresses from the two or more threads being processed by the CPU. The method provides for comparing the AACAM memory address with the active threads to avoid memory hazards by thread switching before the memory hazard occurs.
摘要翻译： 本发明提供一种用于避免共享L-1数据高速缓存的多线程CPU中的存储器危险的系统和方法。 该系统包括一个CPU和一个AACAM。 AACAM能够复制由CPU正在处理的两个或多个线程的内存地址。 该方法用于比较AACAM存储器地址与活动线程，以避免内存危险发生之前通过线程切换的内存危险。
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