公开(公告)号：US5274646A

公开(公告)日：1993-12-28

申请号：US686721

申请日：1991-04-17

申请人： Thomas M. Brey ,  Matthew A. Krygowski ,  Bruce L. McGilvray ,  Trinh H. Nguyen ,  William W. Shen ,  Arthur J. Sutton

发明人： Thomas M. Brey ,  Matthew A. Krygowski ,  Bruce L. McGilvray ,  Trinh H. Nguyen ,  William W. Shen ,  Arthur J. Sutton

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F11/16 ,  G06F12/16

CPC分类号： G06F11/0772 ,  G06F11/073 ,  G06F11/0793 ,  G06F11/1048 ,  G06F11/167

摘要： A method of automatically invoking a recoverable and fault tolerant implementation of the complemented/recomplemented (C/R) error correction method without the assistance of a service processor when an excessive error is detected in main storage (MS) by ECC logic circuits. An excessive error is not correctable by the ECC. These novel changes to the C/R method increase its effectiveness and protect the C/R hardware against random failure. Further, if an excessive error is corrected in a page in MS, an excessive error reporting process is provided for controlling the reporting using a storage map to determine if a previous correction in that page has been reported. If it has been reported, then no further reporting of soft excessive errors is made for that page. A service processor is signaled in parallel to update its persistent copy of the storage map so that on a next initializations of MS the memory map can be restored in the memory. The memory map is used to assist the repair of failing parts of MS, and is reset after MS is repaired.

摘要翻译： 一种在由ECC逻辑电路在主存储器（MS）中检测到过大的错误的情况下，无需服务处理器的协助，自动调用补充/重新补码（C / R）纠错方法的可恢复和容错实现的方法。 ECC不能纠正过大的错误。 C / R方法的这些新变化提高了其有效性，并保护C / R硬件免受随机故障的影响。 此外，如果在MS中的页面中校正了过多的错误，则提供了过多的错误报告处理，用于使用存储映射来控制报告，以确定是否已经报告了该页面中的先前校正。 如果已经报告，则不会再为该页面报告软过度错误。 服务处理器并行发信号以更新其存储映射的持久副本，以便在MS的下一个初始化时，可以在存储器中恢复存储器映射。 存储器映射用于协助修复MS故障部件，并在MS修复后重置。

公开(公告)号：US20090100432A1

公开(公告)日：2009-04-16

申请号：US11871626

申请日：2007-10-12

申请人： David C. Holloway ,  Trinh H. Nguyen ,  Michael D. Snyder ,  Gary L. Whisenhunt

发明人： David C. Holloway ,  Trinh H. Nguyen ,  Michael D. Snyder ,  Gary L. Whisenhunt

IPC分类号： G06F9/46

CPC分类号： G06F9/4881

摘要： A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.

摘要翻译： 处理装置包括：存储部件，被配置为存储与多个线程的相应线程相关联的指令;以及执行单元，被配置为获取并执行指令。 处理装置还包括周期定时器，其包括输出，以响应于周期定时器基于时钟信号达到预定值的计数值来提供指示符。 处理装置还包括多个线程正向进行计数器组件，每个组件被配置成在正在执行对应的线程的指令的同时基于前进进度指示符的发生来调整相应的执行计数器值。 所述处理装置还包括线程选择模块，所述线程选择模块被配置为基于所述周期定时器的状态和所述多个线程前进进程计数器组件中的每一个的状态来选择所述多个线程的线程以由所述执行单元执行。

公开(公告)号：US07805581B2

公开(公告)日：2010-09-28

申请号：US11679590

申请日：2007-02-27

申请人： Michael D. Snyder ,  David C. Holloway ,  Trinh H. Nguyen ,  Sergio Schuler ,  Gary L. Whisenhunt

发明人： Michael D. Snyder ,  David C. Holloway ,  Trinh H. Nguyen ,  Sergio Schuler ,  Gary L. Whisenhunt

IPC分类号： G06F12/00

CPC分类号： G06F9/30181 ,  G06F9/30014 ,  G06F9/30189 ,  G06F9/342

摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。

公开(公告)号：US08117618B2

公开(公告)日：2012-02-14

申请号：US11871626

申请日：2007-10-12

申请人： David C. Holloway ,  Trinh H. Nguyen ,  Michael D. Snyder ,  Gary L. Whisenhunt

发明人： David C. Holloway ,  Trinh H. Nguyen ,  Michael D. Snyder ,  Gary L. Whisenhunt

IPC分类号： G06F9/46

CPC分类号： G06F9/4881

摘要： A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.

摘要翻译： 处理装置包括：存储部件，被配置为存储与多个线程的相应线程相关联的指令;以及执行单元，被配置为获取并执行指令。 处理装置还包括周期定时器，其包括输出，以响应于周期定时器基于时钟信号达到预定值的计数值来提供指示符。 处理装置还包括多个线程正向进行计数器组件，每个组件被配置成在正在执行对应的线程的指令的同时基于前进进度指示符的发生来调整相应的执行计数器值。 所述处理装置还包括线程选择模块，所述线程选择模块被配置为基于所述周期定时器的状态和所述多个线程前进进程计数器组件中的每一个的状态来选择所述多个线程的线程以由所述执行单元执行。

公开(公告)号：US08145942B2

公开(公告)日：2012-03-27

申请号：US12749264

申请日：2010-03-29

申请人： Trinh H. Nguyen

发明人： Trinh H. Nguyen

IPC分类号： G06F11/00

CPC分类号： G06F11/366 ,  G06F11/0748 ,  G06F11/079

摘要： According to one embodiment, a debugging tool includes a processor and logic, that when executed by the processor, causes the processor to: receive a Volume Table of Contents (VTOC)/INDEX data set for a first VTOC/INDEX data of a remote system, create second VTOC/INDEX data (which is a replicated version of the first VTOC/INDEX data of the remote system) from the VTOC/INDEX data set, execute a second scenario (which is a replicated version of a first scenario that was executed on the remote system using the first VTOC/INDEX data that caused the error) using the second VTOC/INDEX data to reproduce an error, and set up trace points in the second VTOC/INDEX data to start a debugging session while executing the second scenario using the second VTOC/INDEX data. Other systems, methods, and computer program products are also described according to various other embodiments.

摘要翻译： 根据一个实施例，调试工具包括处理器和逻辑，当由处理器执行时，该处理器和逻辑使得处理器：接收远程系统的第一VTOC / INDEX数据的卷目录（VTOC）/索引数据集 ，从VTOC / INDEX数据集创建第二个VTOC / INDEX数据（它是远程系统的第一个VTOC / INDEX数据的复制版本），执行第二个场景（这是执行的第一个场景的复制版本） 在远程系统上使用导致错误的第一个VTOC / INDEX数据），使用第二个VTOC / INDEX数据重现错误，并在第二个VTOC / INDEX数据中设置跟踪点，以在执行第二个场景时启动调试会话 使用第二个VTOC / INDEX数据。 还根据各种其他实施例描述其它系统，方法和计算机程序产品。

公开(公告)号：US20110239052A1

公开(公告)日：2011-09-29

申请号：US12749264

申请日：2010-03-29

申请人： Trinh H. Nguyen

发明人： Trinh H. Nguyen

IPC分类号： G06F11/28

CPC分类号： G06F11/366 ,  G06F11/0748 ,  G06F11/079

摘要： According to one embodiment, a debugging tool includes a processor and logic, that when executed by the processor, causes the processor to: receive a Volume Table of Contents (VTOC)/INDEX data set for a first VTOC/INDEX data of a remote system, create second VTOC/INDEX data (which is a replicated version of the first VTOC/INDEX data of the remote system) from the VTOC/INDEX data set, execute a second scenario (which is a replicated version of a first scenario that was executed on the remote system using the first VTOC/INDEX data that caused the error) using the second VTOC/INDEX data to reproduce an error, and set up trace points in the second VTOC/INDEX data to start a debugging session while executing the second scenario using the second VTOC/INDEX data. Other systems, methods, and computer program products are also described according to various other embodiments.

摘要翻译： 根据一个实施例，调试工具包括处理器和逻辑，当由处理器执行时，该处理器和逻辑使得处理器：接收远程系统的第一VTOC / INDEX数据的卷目录（VTOC）/索引数据集 ，从VTOC / INDEX数据集创建第二个VTOC / INDEX数据（它是远程系统的第一个VTOC / INDEX数据的复制版本），执行第二个场景（这是执行的第一个场景的复制版本） 在远程系统上使用导致错误的第一个VTOC / INDEX数据），使用第二个VTOC / INDEX数据重现错误，并在第二个VTOC / INDEX数据中设置跟踪点，以在执行第二个场景时启动调试会话 使用第二个VTOC / INDEX数据。 还根据各种其他实施例描述其它系统，方法和计算机程序产品。

公开(公告)号：US07698353B2

公开(公告)日：2010-04-13

申请号：US11226040

申请日：2005-09-14

申请人： Dimitri Tan ,  Trinh H. Nguyen

发明人： Dimitri Tan ,  Trinh H. Nguyen

IPC分类号： G06F7/00

CPC分类号： G06F7/49936

摘要： A data processor includes a first bit field of a first plurality of bits representing a mantissa of a floating point number and a second bit field of a second plurality of bits representing an exponent of the floating point number. The first plurality of bits is partitioned into a plurality of regions, each of the plurality of regions comprises more than one bit of the first plurality of bits. A leading zero anticipator or other type of leading bit indication circuit is coupled to each region and determines a position of a leading bit of the first plurality of bits. A normalizer is coupled to receive a region of the plurality of regions that contains the leading bit, the normalizer may normalize or denormalize the region to produce a normalized or denormalized floating point number.

摘要翻译： 数据处理器包括表示浮点数的尾数的第一多个比特的第一比特字段和表示浮点数的指数的第二多个比特的第二比特字段。 第一多个比特被划分成多个区域，多个区域中的每一个包括第一多个比特的多于一个比特。 前导零预测器或其他类型的引导位指示电路耦合到每个区域并确定第一多个位的前导位的位置。 归一化器被耦合以接收包含前导位的多个区域的区域，归一化器可以对区域进行归一化或非归一化以产生归一化或非归一化浮点数。

公开(公告)号：US20080209182A1

公开(公告)日：2008-08-28

申请号：US11679590

申请日：2007-02-27

申请人： Michael D. Snyder ,  David C. Holloway ,  Trinh H. Nguyen ,  Sergio Schuler ,  Gary L. Whisenhunt

发明人： Michael D. Snyder ,  David C. Holloway ,  Trinh H. Nguyen ,  Sergio Schuler ,  Gary L. Whisenhunt

IPC分类号： G06F9/302

CPC分类号： G06F9/30181 ,  G06F9/30014 ,  G06F9/30189 ,  G06F9/342

摘要： A data processing device and methods thereof are disclosed. The data processing device can operate in three different modes. In a first, N-bit mode, the data processing device performs memory accesses based on N-bit values and performs arithmetic operations using N-bit values. In a second, hybrid N-bit/M-bit mode, the data processing device performs memory accesses based on M-bit values, where M is less than N, and performs arithmetic operations using N-bit values. In a third, M-bit mode, the data processing device performs memory accesses based on M-bit values and performs arithmetic operations using M-bit values. The three modes provide for compatibility with a wide range of applications. Further operation in the M-bit mode can provide a power savings when implementing applications compatible with that mode.

摘要翻译： 公开了一种数据处理装置及其方法。 数据处理设备可以在三种不同的模式下工作。 在第一N位模式中，数据处理装置根据N位值执行存储器访问，并使用N位值执行算术运算。 在第二种混合N比特/ M比特模式中，数据处理装置基于M比特值执行存储器访问，其中M小于N，并且使用N比特值进行算术运算。 在第三个M位模式中，数据处理设备基于M位值执行存储器访问，并使用M位值执行算术运算。 这三种模式提供与广泛应用的兼容性。 当实现与该模式兼容的应用时，在M位模式下的进一步操作可以提供功率节省。