公开(公告)号：US4972314A

公开(公告)日：1990-11-20

申请号：US218520

申请日：1988-07-05

申请人： Thomas W. Getzinger ,  Hans L. Habereder ,  R. Loyd Harrison ,  Donald M. Hopp ,  David L. Mitchell ,  Chao-Kuang Pian ,  John A. Propster

发明人： Thomas W. Getzinger ,  Hans L. Habereder ,  R. Loyd Harrison ,  Donald M. Hopp ,  David L. Mitchell ,  Chao-Kuang Pian ,  John A. Propster

IPC分类号： G06F13/14

CPC分类号： G06F13/14 ,  G06F9/4436

摘要： A single instruction stream multiple data steam data flow signal processor and method for implementing macro data flow control, in which a plurality of data processors have contentionless access to global memory data. Data processing tasks for the data processors, such as primitive executions together with graph scheduling processes, are developed asynchronously and in parallel from a command program and a macro data flow control graph.

摘要翻译： 单个指令流多个数据流数据流信号处理器和用于实现宏数据流控制的方法，其中多个数据处理器具有无限访问全局存储器数据。 用于数据处理器的数据处理任务，例如原始执行以及图表调度过程，是从命令程序和宏数据流控制图异步并行开发的。

公开(公告)号：US5187795A

公开(公告)日：1993-02-16

申请号：US303790

申请日：1989-01-27

申请人： Kevin D. Balmforth ,  Gary A. Bates ,  Steven P. Davies ,  Hans L. Habereder ,  R. Loyd Harrison ,  Donald M. Hopp ,  George G. Ricker

发明人： Kevin D. Balmforth ,  Gary A. Bates ,  Steven P. Davies ,  Hans L. Habereder ,  R. Loyd Harrison ,  Donald M. Hopp ,  George G. Ricker

IPC分类号： G06F7/00 ,  G06F9/28 ,  G06F15/78 ,  G06F15/80

CPC分类号： G06F15/8092 ,  G06F15/8069 ,  G06F15/8076

摘要： A signal processor comprising a split pipelined parallel processor which processes data signals from external signal sources and provides signal processing functions utilizing a plurality of data formats. The signal processor comprises an external interface unit having a serial control port and a plurality of bidirectional parallel ports. The interface unit transfers control and data signals between the signal processor and external devices. The parallel ports are configurable as individual parallel ports or coupled pairs which form a port having the combined data path of the two coupled ports. An arithmetic element controller comprising a microprogram memory and a control program memory is coupled to the interface unit which loads applications programs into the control program memory and executes the programs. The arithmetic element controller controls the processing of control and data signals in the signal processor. A plurality of pipelined arithmetic elements are coupled to the arithmetic element controller, each comprising a data store memory, a multiplier and a register and arithmetic logic unit. Each arithmetic element has its data store memory coupled to the external interface unit to receive and store data signals, and to its multiplier and the register and arithmetic logic unit in order to perform fixed and floating point arithmetic operations on the data stored in the data store memory. These arithmetic operations are performed in accordance with application program and microprogram instructions contained in the control program and the microprogram memories. The persent invention provides for a high performance architecture for use with vector and matrix signal processing algorithms that minimizes the amount of hardward needed to implement them.