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公开(公告)号：US5532960A
公开(公告)日：1996-07-02
申请号：US371361
申请日：1995-01-11
申请人： Tien-Ler Lin , Liang Chao
发明人： Tien-Ler Lin , Liang Chao
摘要： A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source V.sub.PP. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump including three P-channel type transistors to produce the negative voltage. The source and drain of the first transistor is coupled to the periodic signal. The second transistor's gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.
摘要翻译： 提供一种用于从高正电压源VPP向集成电路提供负高电压的电路。 负电压被施加到多个FLASH电可擦除可编程只读存储器（EPROM）单元。 电路包括耦合到提供周期性信号的电压转换器的振荡器。 周期信号耦合到包括三个P沟道型晶体管的电荷泵以产生负电压。 第一晶体管的源极和漏极耦合到周期性信号。 第二晶体管的栅极和漏极耦合到参考地电位，源极耦合到第一晶体管的栅极。 最后，第三晶体管的漏极和栅极耦合到第一晶体管的栅极，并且第三晶体管的源极在擦除操作期间向多个FLASH EPROM单元的浮动栅极输出负电压。 此外，产生的负电压是相对精确的，因此不需要调节。
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公开(公告)号：US5463586A
公开(公告)日：1995-10-31
申请号：US108670
申请日：1993-08-31
申请人： Liang Chao , Tien-Ler Lin , Tom D. Yiu
发明人： Liang Chao , Tien-Ler Lin , Tom D. Yiu
CPC分类号： G11C29/50008 , G11C16/0491 , G11C16/28 , G11C16/3436 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells and reference cells, and sense circuitry responsive to addressed memory cells and the reference cells, and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory and reference cells is equivalent to adjusting the sense ratio. When the method is applied for program verify, then the second verify potential applied to the reference cell is less than the first verify potential applied to the addressed programmable memory cell. When the method is applied for erase verify, the second verify potential is greater than the first verify potential.
摘要翻译： PCT No.PCT / US93 / 05135 Sec。 371日期：1993年8月31日 102（e）日期1993年8月31日PCT提交1993年5月28日。对于具有存储单元和参考单元的闪存EPROM集成电路的非易失性存储器件以及响应于寻址的存储器单元和参考的感测电路 单元，并且其中读取电位被提供给所选存储单元的栅极，并且参考电位在读取模式期间被提供给参考存储单元的栅极，可编程存储单元的状态通过（1） 向地址可编程存储单元的门提供第一验证电位; 和（2）向与第一验证电位不同的参考单元的栅极提供第二验证电位。 因为电池电流是栅极电压的非常强的功能，所以对存储器和参考电池施加不同的栅极电压等同于调整感测比。 当该方法应用于程序验证时，施加到参考单元的第二验证电位小于施加到寻址的可编程存储器单元的第一验证电位。 当该方法应用于擦除验证时，第二验证电位大于第一验证电位。
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公开(公告)号：US5544116A
公开(公告)日：1996-08-06
申请号：US444672
申请日：1995-05-19
申请人： Liang Chao , Tien-Ler Lin , Tom D. Yiu
发明人： Liang Chao , Tien-Ler Lin , Tom D. Yiu
CPC分类号： G11C29/50008 , G11C16/0491 , G11C16/28 , G11C16/3436 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells and reference cells, and sense circuitry responsive to addressed memory cells and the reference cells, and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory and reference cells is equivalent to adjusting the sense ratio. When the method is applied for program verify, then the second verify potential applied to the reference cell is less than the first verify potential applied to the addressed programmable memory cell. When the method is applied for erase verify, the second verify potential is greater than the first verify potential.
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公开(公告)号：US5528546A
公开(公告)日：1996-06-18
申请号：US444771
申请日：1995-05-19
申请人： Liang Chao , Tien-Ler Lin , Tom D.-H. Yiu
发明人： Liang Chao , Tien-Ler Lin , Tom D.-H. Yiu
CPC分类号： G11C29/50008 , G11C16/0491 , G11C16/28 , G11C16/3436 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： For non-volatile memory devices, such as flash EPROM integrated circuits, which have memory cells and reference cells, and sense circuitry responsive to addressed memory cells and the reference cells, and in which a read potential is supplied to the gate of the selected memory cells and a reference potential is supplied to the gate of a reference memory cell during a read mode, the state of the programmable memory cells is verified by (1) supplying a first verify potential to the gate of an address programmable memory cell; and (2) supplying a second verify potential to the gate of the reference cell which is different from the first verify potential. Because cell current is a very strong function of the gate voltage, applying different gate voltages to the memory and reference cells is equivalent to adjusting the sense ratio. When the method is applied for program verify, then the second verify potential applied to the reference cell is less than the first verify potential applied to the addressed programmable memory cell. When the method is applied for erase verify, the second verify potential is greater than the first verify potential.
摘要翻译： 对于具有存储单元和参考单元的诸如闪存EPROM集成电路的非易失性存储器件以及响应于寻址的存储器单元和参考单元的读出电路，并且其中读取电位被提供给所选择的存储器的门 在读取模式期间将单元和参考电位提供给参考存储单元的栅极，通过（1）向地址可编程存储单元的栅极提供第一验证电位来验证可编程存储单元的状态; 和（2）向与第一验证电位不同的参考单元的栅极提供第二验证电位。 因为电池电流是栅极电压的非常强的功能，所以对存储器和参考电池施加不同的栅极电压等同于调整感测比。 当该方法应用于程序验证时，施加到参考单元的第二验证电位小于施加到寻址的可编程存储器单元的第一验证电位。 当该方法应用于擦除验证时，第二验证电位大于第一验证电位。
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公开(公告)号：US5399928A
公开(公告)日：1995-03-21
申请号：US108647
申请日：1993-08-31
申请人： Tien-Ler Lin , Liang Chao
发明人： Tien-Ler Lin , Liang Chao
摘要： A circuit is provided for supplying a negative high voltage to an integrated circuit from a high positive voltage source V.sub.PP. The negative voltage is applied to a plurality of FLASH electrically erasable programmable read only memory (EPROM) cells. The circuit includes an oscillator coupled to a voltage converter which provides a periodic signal. The periodic signal is coupled to a charge pump including three P-channel type transistors to produce the negative voltage. The source and drain of the first transistor is coupled to the periodic signal. The second transistor's gate and drain is coupled to a reference ground potential with the source coupled to the first transistor's gate. Finally, the third transistor's drain and gate is coupled to the first transistor's gate and the third transistor's source outputs negative voltage to floating gates of the plurality of FLASH EPROM cells during an erase operation. Further, the negative voltage generated is relatively precise, so no regulation is required.
摘要翻译： PCT No.PCT / US93 / 05133 Sec。 371日期：1993年8月31日 102（e）日期1993年8月31日PCT提交1993年5月28日PCT公布。 出版物WO94 / 28629 日期1994年12月8日。提供一种用于从高正电压源VPP向集成电路提供负高电压的电路。 负电压被施加到多个FLASH电可擦除可编程只读存储器（EPROM）单元。 电路包括耦合到提供周期性信号的电压转换器的振荡器。 周期信号耦合到包括三个P沟道型晶体管的电荷泵以产生负电压。 第一晶体管的源极和漏极耦合到周期性信号。 第二晶体管的栅极和漏极耦合到参考地电位，源极耦合到第一晶体管的栅极。 最后，第三晶体管的漏极和栅极耦合到第一晶体管的栅极，并且第三晶体管的源极在擦除操作期间向多个FLASH EPROM单元的浮动栅极输出负电压。 此外，产生的负电压是相对精确的，因此不需要调节。
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