公开(公告)号：US06924689B2

公开(公告)日：2005-08-02

申请号：US10166309

申请日：2002-06-10

申请人： Todd A. Randazzo ,  E. Wayne Porter

发明人： Todd A. Randazzo ,  E. Wayne Porter

IPC分类号： G05F3/24 ,  H03K3/356 ,  H03L5/00

CPC分类号： G05F3/242 ,  H03K3/356113 ,  H03K3/356147

摘要： A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value.

摘要翻译： 用于输入使用参考电压源的输出电压电平移位器的核心电压以产生参考电压，以限制连接到电压敏感开关器件的至少一个电压敏感节点上的漏极电压，所述电压敏感节点位于高电压域 。 反馈线从电压敏感节点延伸到参考电压源。 反馈结构响应于至少一个电压敏感节点上的漏极电压而改变参考电压，从而将漏极电压维持在基本恒定的期望值。

公开(公告)号：US5592113A

公开(公告)日：1997-01-07

申请号：US412270

申请日：1995-03-28

申请人： Duane G. Quiet ,  E. Wayne Porter

发明人： Duane G. Quiet ,  E. Wayne Porter

IPC分类号： H03D13/00 ,  H03L7/089 ,  H03L7/183 ,  H03L7/06

CPC分类号： H03L7/0895 ,  H03D13/004 ,  H03L7/0891 ,  H03L7/183

摘要： An error-limiting circuit for regulating the time required to bring the output signal of a control system such as a phase-locked loop device into conformance with a reference input signal. For a phase-locked loop system the error-limiting circuit is a phase-error-limiting circuit that provides for a gradual changing of the signal frequency of a voltage-controlled oscillator of the phase-locked loop device so that frequency synchronization of subsequent devices coupled to the phase-locked loop with the reference signal is ensured. The phase-error-limiting circuit forms part of the phase-frequency detector that is coupled to a charge pump that outputs current to a loop filter that in turn effectively controls the voltage-controlled oscillator. The phase-error-limiting circuit acts to assert or de-assert as required an error-correcting UP or DOWN signal to the charge pump. While the charge supplied by the charge pump is normally dependent only on the phase difference between the reference signal and the VCO signal, the phase-error-limiting circuit cuts in to control the UP or DOWN signal duration when the phase difference exceeds some pre-selected value. The phase-error-limiting circuit thereby clips the charge that can be supplied by the charge pump and thereby slows the move of the voltage-controlled oscillator frequency to the reference signal frequency.

摘要翻译： 用于调节使诸如锁相环装置之类的控制系统的输出信号符合参考输入信号所需的时间的误差限制电路。 对于锁相环系统，误差限制电路是相位误差限制电路，其提供锁相环装置的压控振荡器的信号频率的逐渐改变，使得后续装置的频率同步 确保了与参考信号的锁相环耦合。 相位误差限制电路构成了相位频率检测器的一部分，其耦合到电荷泵，该电荷泵将电流输出到环路滤波器，该环路滤波器又有效地控制压控振荡器。 相位误差限制电路根据需要对电荷泵进行纠错UP或DOWN信号的断言或解除置位。 虽然由电荷泵提供的电荷通常仅取决于参考信号和VCO信号之间的相位差，但是当相位差超过一些预定值时，相位误差限制电路切入以控制UP或DOWN信号持续时间， 选定值。 因此，相位误差限制电路剪切可由电荷泵提供的电荷，从而减缓压控振荡器频率与参考信号频率的移动。