Off Chip Memory for Distributed Tessellation
    1.
    发明申请
    Off Chip Memory for Distributed Tessellation 有权
    用于分布式镶嵌的片外存储器

    公开(公告)号:US20130169634A1

    公开(公告)日:2013-07-04

    申请号:US13449410

    申请日:2012-04-18

    IPC分类号: G06T17/20

    CPC分类号: G06T17/20 G06T15/005

    摘要: Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.

    摘要翻译: 实施例包括一种装置,计算机可读介质和用于在包括至少两个计算单元的加速处理装置(APD)内分配镶嵌的方法。 实施例包括使用船体着色器在第一计算单元中处理多个补丁以生成船体着色器输出数据。 一旦生成,当与着色器程序相关联的细分因素大于配置的阈值时,将船体着色器输出数据存储到片外存储器中。 一旦存储在片外存储器中,使用第二计算单元动态地处理至少一部分船体着色器输出数据。

    Tessellation Patterns
    2.
    发明申请
    Tessellation Patterns 有权
    镶嵌模式

    公开(公告)号:US20130162651A1

    公开(公告)日:2013-06-27

    申请号:US13336635

    申请日:2011-12-23

    IPC分类号: G06T11/20

    CPC分类号: G06T17/20

    摘要: Methods, systems, and computer readable media embodiments are disclosed for generating primitives in a grid. Embodiments include generating a set of vertices in a section of the grid, selecting one or more vertices in the set of vertices in an order based on a proximity of the vertices to a boundary edge of the grid, and generating primitives based on the order of the selected vertices.

    摘要翻译: 公开了用于在网格中生成图元的方法,系统和计算机可读介质实施例。 实施例包括在网格的一部分中生成一组顶点,基于顶点到网格的边界边缘的顺序,以一定顺序选择顶点集合中的一个或多个顶点,并且基于网格的顺序生成图元 所选顶点。

    Off chip memory for distributed tessellation
    3.
    发明授权
    Off chip memory for distributed tessellation 有权
    用于分布式镶嵌的片外存储器

    公开(公告)号:US09390554B2

    公开(公告)日:2016-07-12

    申请号:US13449410

    申请日:2012-04-18

    IPC分类号: G06T15/30 G06T17/20 G06T15/00

    CPC分类号: G06T17/20 G06T15/005

    摘要: Embodiments include an apparatus, a computer readable medium and a method for distributing tessellations within an accelerated processing device (APD) including at least two compute units. Embodiments include processing a plurality of patches in a first compute unit using a hull shader to generate hull shader output data. Once generated, hull shader output data is stored to an off-chip memory when tessellation factors associated with the shader program are greater than a configured threshold. Once stored in the off-chip memory, at least a portion of the hull shader output data is dynamically processed using a second compute unit.

    摘要翻译: 实施例包括一种装置,计算机可读介质和用于在包括至少两个计算单元的加速处理装置(APD)内分配镶嵌的方法。 实施例包括使用船体着色器在第一计算单元中处理多个补丁以生成船体着色器输出数据。 一旦生成,当与着色器程序相关联的细分因素大于配置的阈值时,将船体着色器输出数据存储到片外存储器中。 一旦存储在片外存储器中,使用第二计算单元动态地处理至少一部分船体着色器输出数据。

    Tessellation patterns
    4.
    发明授权
    Tessellation patterns 有权
    镶嵌图案

    公开(公告)号:US08854374B2

    公开(公告)日:2014-10-07

    申请号:US13336635

    申请日:2011-12-23

    IPC分类号: G06T11/20

    CPC分类号: G06T17/20

    摘要: Methods, systems, and computer readable media embodiments are disclosed for generating primitives in a grid. Embodiments include generating a set of vertices in a section of the grid, selecting one or more vertices in the set of vertices in an order based on a proximity of the vertices to a boundary edge of the grid, and generating primitives based on the order of the selected vertices.

    摘要翻译: 公开了用于在网格中生成图元的方法,系统和计算机可读介质实施例。 实施例包括在网格的一部分中生成一组顶点,基于顶点到网格的边界边缘的顺序,以一定顺序选择顶点集合中的一个或多个顶点,并且基于网格的顺序生成图元 所选顶点。

    Data Processing Using On-Chip Memory In Multiple Processing Units
    5.
    发明申请
    Data Processing Using On-Chip Memory In Multiple Processing Units 审中-公开
    在多处理单元中使用片上存储器的数据处理

    公开(公告)号:US20120017062A1

    公开(公告)日:2012-01-19

    申请号:US13186038

    申请日:2011-07-19

    IPC分类号: G06F15/76 G06F9/06 G06F12/02

    摘要: Methods are disclosed for improving data processing performance in a processor using on-chip local memory in multiple processing units. According to an embodiment, a method of processing data elements in a processor using a plurality of processing units, includes: launching, in each of the processing units, a first wavefront having a first type of thread followed by a second wavefront having a second type of thread, where the first wavefront reads as input a portion of the data elements from an off-chip shared memory and generates a first output; writing the first output to an on-chip local memory of the respective processing unit; and writing to the on-chip local memory a second output generated by the second wavefront, where input to the second wavefront comprises a first plurality of data elements from the first output. Corresponding system and computer program product embodiments are also disclosed.

    摘要翻译: 公开了用于在多个处理单元中使用片上本地存储器来改善处理器中的数据处理性能的方法。 根据实施例,一种使用多个处理单元处理处理器中的数据元素的方法包括:在每个处理单元中发射具有第一类型线程的第一波前面,之后是具有第二类型的第二波阵面 的线程,其中第一波前从片外共享存储器读取数据元素的一部分作为输入,并产生第一输出; 将第一输出写入相应处理单元的片上本地存储器; 以及向所述片上本地存储器写入由所述第二波前产生的第二输出,其中到所述第二波阵面的输入包括来自所述第一输出的第一多个数据元素。 还公开了相应的系统和计算机程序产品实施例。

    Variable frequency output to one or more buffers
    6.
    发明授权
    Variable frequency output to one or more buffers 有权
    可变频率输出到一个或多个缓冲器

    公开(公告)号:US09244690B2

    公开(公告)日:2016-01-26

    申请号:US12878667

    申请日:2010-09-09

    IPC分类号: G06F9/38 G06F15/17 G06T1/00

    CPC分类号: G06F9/3851 G06F15/17 G06T1/00

    摘要: A system and method are presented by which data on a graphics processing unit (GPU) can be output to one or more buffers with independent output frequencies. In one embodiment, a GPU includes a shader processor configured to respectively emit a plurality of data sets into a plurality of streams in parallel. Each data is emitted into at least a portion of its respective stream. Also included is a first number of counters configured to respectively track the emitted data sets.

    摘要翻译: 提出了一种系统和方法,其中图形处理单元(GPU)上的数据可以被输出到具有独立输出频率的一个或多个缓冲器。 在一个实施例中,GPU包括着色器处理器,其被配置为并行地将多个数据集分别发射成多个流。 每个数据被发射到其相应流的至少一部分。 还包括配置为分别跟踪发射的数据集的第一数量的计数器。

    Merged shader for primitive amplification
    7.
    发明授权
    Merged shader for primitive amplification 有权
    合并着色器进行原始放大

    公开(公告)号:US08259111B2

    公开(公告)日:2012-09-04

    申请号:US12185474

    申请日:2008-08-04

    IPC分类号: G06T15/50 G06T15/10 G06T1/20

    CPC分类号: G06T15/005

    摘要: A method, computer program product, and system are provided for processing data in a graphics pipeline. An embodiment of the method includes processing one or more vertices of a geometric primitive with a vertex shader function and generating new primitive information for the one or more processed vertices with a geometry shader function. The geometry shader function receives one or more processed vertices from the vertex shader function and emits a single vertex associated with the new primitive information. Each emitted vertex from the geometry shader function can be stored in a memory device. Unlike conventional graphic pipelines that require a memory device for data storage during the vertex and geometry shading processes, the present invention increases efficiency in the graphics pipeline by eliminating the need to access memory when the vertex and geometry shaders process vertex information.

    摘要翻译: 提供了一种用于在图形管线中处理数据的方法,计算机程序产品和系统。 该方法的一个实施例包括使用顶点着色器功能处理几何基元的一个或多个顶点,并使用几何着色器功能为一个或多个经处理的顶点生成新的基元信息。 几何着色器功能从顶点着色器功能接收一个或多个经处理的顶点,并发出与新的基元信息相关联的单个顶点。 来自几何着色器功能的每个发出的顶点都可以存储在存储设备中。 与在顶点和几何着色处理期间需要用于数据存储的存储器件的传统图形流水线不同,本发明通过在顶点和几何着色器处理顶点信息时消除对存储器的访问来提高图形流水线的效率。

    Variable Frequency Output To One Or More Buffers
    8.
    发明申请
    Variable Frequency Output To One Or More Buffers 有权
    变频输出到一个或多个缓冲器

    公开(公告)号:US20110057938A1

    公开(公告)日:2011-03-10

    申请号:US12878667

    申请日:2010-09-09

    IPC分类号: G06F15/80 G06F9/302 G06F9/305

    CPC分类号: G06F9/3851 G06F15/17 G06T1/00

    摘要: A system and method are presented by which data on a graphics processing unit (GPU) can be output to one or more buffers with independent output frequencies. In one embodiment, a GPU includes a shader processor configured to respectively emit a plurality of data sets into a plurality of streams in parallel. Each data is emitted into at least a portion of its respective stream. Also included is a first number of counters configured to respectively track the emitted data sets.

    摘要翻译: 提出了一种系统和方法,其中图形处理单元(GPU)上的数据可以被输出到具有独立输出频率的一个或多个缓冲器。 在一个实施例中,GPU包括着色器处理器,其被配置为并行地将多个数据集分别发射成多个流。 每个数据被发射到其相应流的至少一部分。 还包括配置为分别跟踪发射的数据集的第一数量的计数器。

    Merged Shader for Primitive Amplification
    9.
    发明申请
    Merged Shader for Primitive Amplification 有权
    合并着色器进行原始放大

    公开(公告)号:US20090295804A1

    公开(公告)日:2009-12-03

    申请号:US12185474

    申请日:2008-08-04

    IPC分类号: G06T15/50

    CPC分类号: G06T15/005

    摘要: A method, computer program product, and system are provided for processing data in a graphics pipeline. An embodiment of the method includes processing one or more vertices of a geometric primitive with a vertex shader function and generating new primitive information for the one or more processed vertices with a geometry shader function. The geometry shader function receives one or more processed vertices from the vertex shader function and emits a single vertex associated with the new primitive information. Each emitted vertex from the geometry shader function can be stored in a memory device. Unlike conventional graphic pipelines that require a memory device for data storage during the vertex and geometry shading processes, the present invention increases efficiency in the graphics pipeline by eliminating the need to access memory when the vertex and geometry shaders process vertex information.

    摘要翻译: 提供了一种用于在图形管线中处理数据的方法,计算机程序产品和系统。 该方法的一个实施例包括使用顶点着色器功能处理几何基元的一个或多个顶点,并使用几何着色器功能为一个或多个经处理的顶点生成新的基元信息。 几何着色器功能从顶点着色器功能接收一个或多个经处理的顶点,并发出与新的基元信息相关联的单个顶点。 来自几何着色器功能的每个发出的顶点都可以存储在存储设备中。 与在顶点和几何着色处理期间需要用于数据存储的存储器件的传统图形流水线不同,本发明通过在顶点和几何着色器处理顶点信息时消除对存储器的访问来提高图形流水线的效率。