公开(公告)号：US20180286476A1

公开(公告)日：2018-10-04

申请号：US15476654

申请日：2017-03-31

申请人： Tommaso VALI ,  Violante MOSCHIANO ,  Andrea D'ALESSANDRO ,  Pranav KALAVADE

发明人： Tommaso VALI ,  Violante MOSCHIANO ,  Andrea D'ALESSANDRO ,  Pranav KALAVADE

IPC分类号： G11C11/56 ,  G11C16/10 ,  G11C16/34

摘要： An apparatus is described. The apparatus includes a non volatile memory device that includes a controller to implement a coarse write process for the non volatile memory device. The non volatile memory device includes storage cells to store more than two logic states, wherein, the coarse write process is to perform a verify operation early in the coarse write process to identify less responsive storage cells and provide additional charge to the less responsive storage cells as compared to non less responsive storage cells that are to be programmed to a same logical state as the less responsive storage cells without performing a following verify operation after each pulse of charge applied during the coarse write process.