公开(公告)号：US08223569B2

公开(公告)日：2012-07-17

申请号：US12836851

申请日：2010-07-15

申请人： Tomoyuki Hamano ,  Shigefumi Ishiguro ,  Toshifumi Watanabe ,  Kazuto Uehara

发明人： Tomoyuki Hamano ,  Shigefumi Ishiguro ,  Toshifumi Watanabe ,  Kazuto Uehara

IPC分类号： G11C7/00

CPC分类号： G11C8/04 ,  G11C11/41 ,  G11C2029/0411

摘要： According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器阵列，地址计数器，地址检测电路和控制电路。 存储器阵列具有布置在字线和位线的交叉位置处的多个存储单元。 地址计数器与时钟同步地增加包括行地址和列地址的地址，以顺序输出递增的地址。 地址检测电路在从地址计数器输出的地址处检测包括行地址切换到的行地址的地址，以输出检测信号。 控制电路根据从地址检测电路输出的检测信号对与存储单元连接的位线执行预充电操作。

公开(公告)号：US08259523B2

公开(公告)日：2012-09-04

申请号：US12836944

申请日：2010-07-15

申请人： Toshifumi Watanabe ,  Tomoyuki Hamano ,  Shigefumi Ishiguro ,  Kazuto Uehara

发明人： Toshifumi Watanabe ,  Tomoyuki Hamano ,  Shigefumi Ishiguro ,  Kazuto Uehara

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C8/12 ,  G11C11/005

摘要： According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.

摘要翻译： 根据一个实施例，半导体存储器件包括第一存储器，第二存储器和控制电路。 第一存储器包括第一个银行号码。 第二存储器包括大于第一存储体号的第二存储体号。 控制电路相对于设置在第一和第二存储器中的位线控制预充电操作。 当相对于第一存储器执行与时钟同步地进行的同步操作时，控制电路在初始化结束时间段内将第二预充电操作改变为与第一预充电操作不同的操作时间 在接收地址之后的第二预充电操作开始的第一预充电操作。

公开(公告)号：US20110013472A1

公开(公告)日：2011-01-20

申请号：US12836851

申请日：2010-07-15

申请人： Tomoyuki HAMANO ,  Shigefumi Ishiguro ,  Toshifumi Watanabe ,  Kazuto Uehara

发明人： Tomoyuki HAMANO ,  Shigefumi Ishiguro ,  Toshifumi Watanabe ,  Kazuto Uehara

IPC分类号： G11C8/00 ,  G11C8/04

CPC分类号： G11C8/04 ,  G11C11/41 ,  G11C2029/0411

摘要： According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器阵列，地址计数器，地址检测电路和控制电路。 存储器阵列具有布置在字线和位线的交叉位置处的多个存储单元。 地址计数器与时钟同步地增加包括行地址和列地址的地址，以顺序输出递增的地址。 地址检测电路在从地址计数器输出的地址处检测包括行地址切换到的行地址的地址，以输出检测信号。 控制电路根据从地址检测电路输出的检测信号对与存储单元连接的位线执行预充电操作。

公开(公告)号：US08189424B2

公开(公告)日：2012-05-29

申请号：US12397711

申请日：2009-03-04

申请人： Kazuto Uehara ,  Toshifumi Watanabe ,  Shigefumi Ishiguro ,  Kazuyoshi Muraoka

发明人： Kazuto Uehara ,  Toshifumi Watanabe ,  Shigefumi Ishiguro ,  Kazuyoshi Muraoka

IPC分类号： G11C8/00

CPC分类号： G11C7/1027 ,  G11C7/1006 ,  G11C7/1039 ,  G11C11/005 ,  G11C2029/0411

摘要： A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.

摘要翻译： 配置为执行时钟同步突发读取操作的半导体存储器件包括具有不同库结构的多个缓冲存储器，以及存储从多个缓冲存储器读取的读取数据的第一和第二数据锁存电路。 半导体存储装置还包括控制电路，其根据缓冲器的存储体结构，在时钟同步脉冲串读取操作时控制开始计数上升地址的定时和在第一数据锁存电路中存储读取数据的定时 存储器作为读操作目标。