公开(公告)号：US08189424B2

公开(公告)日：2012-05-29

申请号：US12397711

申请日：2009-03-04

申请人： Kazuto Uehara ,  Toshifumi Watanabe ,  Shigefumi Ishiguro ,  Kazuyoshi Muraoka

发明人： Kazuto Uehara ,  Toshifumi Watanabe ,  Shigefumi Ishiguro ,  Kazuyoshi Muraoka

IPC分类号： G11C8/00

CPC分类号： G11C7/1027 ,  G11C7/1006 ,  G11C7/1039 ,  G11C11/005 ,  G11C2029/0411

摘要： A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.

摘要翻译： 配置为执行时钟同步突发读取操作的半导体存储器件包括具有不同库结构的多个缓冲存储器，以及存储从多个缓冲存储器读取的读取数据的第一和第二数据锁存电路。 半导体存储装置还包括控制电路，其根据缓冲器的存储体结构，在时钟同步脉冲串读取操作时控制开始计数上升地址的定时和在第一数据锁存电路中存储读取数据的定时 存储器作为读操作目标。

公开(公告)号：US20090316494A1

公开(公告)日：2009-12-24

申请号：US12397711

申请日：2009-03-04

申请人： Kazuto UEHARA ,  Toshifumi Watanabe ,  Shigefumi Ishiguro ,  Kazuyoshi Muraoka

发明人： Kazuto UEHARA ,  Toshifumi Watanabe ,  Shigefumi Ishiguro ,  Kazuyoshi Muraoka

IPC分类号： G11C7/10 ,  G11C8/18 ,  G11C7/00

CPC分类号： G11C7/1027 ,  G11C7/1006 ,  G11C7/1039 ,  G11C11/005 ,  G11C2029/0411

摘要： A semiconductor memory device configured to perform a clock synchronous burst read operation includes a plurality of buffer memories having different bank structures, and first and second data latch circuits storing read data read from the plurality of buffer memories. The semiconductor memory device further includes a control circuit that controls a timing of starting counting up addresses and a timing of storing read data in the first data latch circuit at the time of the clock synchronous burst read operation in accordance with the bank structure of the buffer memory as a read operation target.

摘要翻译： 配置为执行时钟同步突发读取操作的半导体存储器件包括具有不同库结构的多个缓冲存储器，以及存储从多个缓冲存储器读取的读取数据的第一和第二数据锁存电路。 半导体存储装置还包括控制电路，其根据缓冲器的存储体结构，在时钟同步脉冲串读取操作时控制开始计数上升地址的定时和在第一数据锁存电路中存储读取数据的定时 存储器作为读操作目标。

公开(公告)号：US08223569B2

公开(公告)日：2012-07-17

申请号：US12836851

申请日：2010-07-15

申请人： Tomoyuki Hamano ,  Shigefumi Ishiguro ,  Toshifumi Watanabe ,  Kazuto Uehara

发明人： Tomoyuki Hamano ,  Shigefumi Ishiguro ,  Toshifumi Watanabe ,  Kazuto Uehara

IPC分类号： G11C7/00

CPC分类号： G11C8/04 ,  G11C11/41 ,  G11C2029/0411

摘要： According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器阵列，地址计数器，地址检测电路和控制电路。 存储器阵列具有布置在字线和位线的交叉位置处的多个存储单元。 地址计数器与时钟同步地增加包括行地址和列地址的地址，以顺序输出递增的地址。 地址检测电路在从地址计数器输出的地址处检测包括行地址切换到的行地址的地址，以输出检测信号。 控制电路根据从地址检测电路输出的检测信号对与存储单元连接的位线执行预充电操作。

公开(公告)号：US08259523B2

公开(公告)日：2012-09-04

申请号：US12836944

申请日：2010-07-15

申请人： Toshifumi Watanabe ,  Tomoyuki Hamano ,  Shigefumi Ishiguro ,  Kazuto Uehara

发明人： Toshifumi Watanabe ,  Tomoyuki Hamano ,  Shigefumi Ishiguro ,  Kazuto Uehara

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C8/12 ,  G11C11/005

摘要： According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.

摘要翻译： 根据一个实施例，半导体存储器件包括第一存储器，第二存储器和控制电路。 第一存储器包括第一个银行号码。 第二存储器包括大于第一存储体号的第二存储体号。 控制电路相对于设置在第一和第二存储器中的位线控制预充电操作。 当相对于第一存储器执行与时钟同步地进行的同步操作时，控制电路在初始化结束时间段内将第二预充电操作改变为与第一预充电操作不同的操作时间 在接收地址之后的第二预充电操作开始的第一预充电操作。

公开(公告)号：US20110013472A1

公开(公告)日：2011-01-20

申请号：US12836851

申请日：2010-07-15

申请人： Tomoyuki HAMANO ,  Shigefumi Ishiguro ,  Toshifumi Watanabe ,  Kazuto Uehara

发明人： Tomoyuki HAMANO ,  Shigefumi Ishiguro ,  Toshifumi Watanabe ,  Kazuto Uehara

IPC分类号： G11C8/00 ,  G11C8/04

CPC分类号： G11C8/04 ,  G11C11/41 ,  G11C2029/0411

摘要： According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.

摘要翻译： 根据一个实施例，半导体存储器件包括存储器阵列，地址计数器，地址检测电路和控制电路。 存储器阵列具有布置在字线和位线的交叉位置处的多个存储单元。 地址计数器与时钟同步地增加包括行地址和列地址的地址，以顺序输出递增的地址。 地址检测电路在从地址计数器输出的地址处检测包括行地址切换到的行地址的地址，以输出检测信号。 控制电路根据从地址检测电路输出的检测信号对与存储单元连接的位线执行预充电操作。

公开(公告)号：US07577058B2

公开(公告)日：2009-08-18

申请号：US11774919

申请日：2007-07-09

申请人： Toshifumi Watanabe ,  Shigefumi Ishiguro

发明人： Toshifumi Watanabe ,  Shigefumi Ishiguro

IPC分类号： G11C8/00

CPC分类号： H03K19/017509 ,  H03K5/19

摘要： A semiconductor device includes a first input terminal, the first input terminal being supplied with an input signal, an input detection circuit including a delay circuit having a second input terminal and an output terminal, the input detection circuit detecting a shift in the input signal and generating a first pulse signal in response to the shift, the input detection circuit being connected to the first input terminal, and a control circuit for generating control signals, each of the control signals being generated in response to a synchronous operation or an asynchronous operation respectively.

摘要翻译： 一种半导体器件，包括：第一输入端子，第一输入端子被提供有输入信号;输入检测电路，包括具有第二输入端子和输出端子的延迟电路;输入检测电路检测输入信号的偏移;以及 响应于偏移产生第一脉冲信号，输入检测电路连接到第一输入端子，以及用于产生控制信号的控制电路，每个控制信号分别响应于同步操作或异步操作产生 。

公开(公告)号：US5208780A

公开(公告)日：1993-05-04

申请号：US731467

申请日：1991-07-17

申请人： Taira Iwase ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuhiko Nobori

发明人： Taira Iwase ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuhiko Nobori

IPC分类号： G11C17/16 ,  G11C29/00

CPC分类号： G11C29/835 ,  G11C17/16

摘要： In an electrically programmable ROM, each cell 13 includes a series-connected element composed of a combination writing and reading transistor 17 and a fuse 15. One end of this series-connected element is connected to a corresponding bit line 19, and the other end thereof is grounded. A gate of the transistor 17 of the series-connected element is connected to a corresponding word line 23. Each bit line 19 is connected to a high-voltage applying pad 21 via an element such as diode or transistor provided with electrically connecting/isolating functions. When a data is written in the memory cell 13, the high-voltage applying pad 21 is electrically connected to the bit line 19. Under these conditions, if a high voltage is applied to the high-voltage applying pad 21, the transistor 17 performs snap-back action (i.e. secondary breakdown) to blow out the fuse 15. When the data is read, the high-voltage applying pad 21 is isolated from the bit line 19 without exerting influence upon the read out operation. In addition, in the above-mentioned electrically programmable ROM, a circuit for electrically blowing out the fuse by utilizing transistor's snap-back action is used as a redundancy signature indicative of whether the redundancy circuit is used or unused.

摘要翻译： 在电可编程ROM中，每个单元13包括由写入和读取晶体管17和熔丝15组成的串联元件。该串联元件的一端连接到对应的位线19，而另一端 它接地。 串联元件的晶体管17的栅极连接到相应的字线23.每个位线19经由诸如具有电连接/隔离功能的二极管或晶体管的元件连接到高压施加焊盘21 。 当数据被写入存储单元13时，高压施加焊盘21与位线19电连接。在这些条件下，如果向高压施加焊盘21施加高电压，则晶体管17执行 回扫动作（即二次击穿）以吹出保险丝15.当读取数据时，高压施加垫21与位线19隔离，而不会对读出操作产生影响。 此外，在上述电气可编程ROM中，使用用于通过利用晶体管的快速恢复动作来电熔熔丝的电路作为指示冗余电路是否被使用或未被使用的冗余标记。

公开(公告)号：US20080253198A1

公开(公告)日：2008-10-16

申请号：US11865483

申请日：2007-10-01

申请人： Tomoyuki Hamano ,  Shigefumi Ishiguro

发明人： Tomoyuki Hamano ,  Shigefumi Ishiguro

IPC分类号： G11C7/10 ,  G11C7/02

CPC分类号： G11C7/02 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/06 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4082 ,  G11C11/4093

摘要： A semiconductor memory device includes a memory cell array, an output buffer circuit and an input buffer circuit. The memory cell array includes a plurality of memory cells holding data. The output buffer circuit outputs data read from the memory cells. The input buffer circuit receives an address signal for the memory cells and includes a noise filter to remove noise. The filter length of the noise filter is variable according to the output capability of the data in the output buffer circuit.

摘要翻译： 半导体存储器件包括存储单元阵列，输出缓冲电路和输入缓冲电路。 存储单元阵列包括保存数据的多个存储单元。 输出缓冲电路输出从存储单元读出的数据。 输入缓冲电路接收存储单元的地址信号，并且包括用于去除噪声的噪声滤波器。 噪声滤波器的滤波器长度根据输出缓冲电路中数据的输出能力而变化。

公开(公告)号：US5257230A

公开(公告)日：1993-10-26

申请号：US565820

申请日：1990-08-13

申请人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

发明人： Kazuhiko Nobori ,  Taira Iwase ,  Masamichi Asano ,  Makoto Takizawa ,  Shigefumi Ishiguro ,  Kazuo Yonehara ,  Satoshi Nikawa ,  Koji Saito

IPC分类号： H01L21/82 ,  G11C29/00 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/10 ,  G11C17/16

CPC分类号： G11C29/785 ,  H01L23/5256 ,  H01L27/1126 ,  H01L2924/0002

摘要： There is disclosed an improved semiconductor memory device having a regular memory cell array and a spare memory cell array. Each spare memory cell constituting the spare memory cell array includes a first transistor selected by a read word line, whose drain is connected to a spare bit line and source is connected via a fuse to a power supply, and a second transistor connected between the interconnection between the first transistor and fuse and a ground. The fuse is selectively blown by flowing a blowing current through the fuse by selecting the second transistor through a write line to thereby disconnect a discharge current path of the spare bit line. The threshold voltage of the second transistor of the spare memory cell which is made conductive upon selection by the write line when the blowing current flows through the fuse is higher than a potential difference between a potential generated at the write line connected with another spare memory cell and a ground potential. Such a high threshold voltage is obtained by including in manufacture of the memory cell the steps of implanting impurity ions of a first conductivity type to the channel area of a region on the surface of a semiconductor substrate where transistors including the second transistor of a second conductivity type different from the first conductivity type are formed; and implanting impurity ions of the one conductivity type to the channel area of the second transistor and to the channel area of transistors of a conductivity type different from the second transistor; whereby the impurity ions are implanted twice to the channel area of the second transistor.

公开(公告)号：US07606083B2

公开(公告)日：2009-10-20

申请号：US11865483

申请日：2007-10-01

申请人： Tomoyuki Hamano ,  Shigefumi Ishiguro

发明人： Tomoyuki Hamano ,  Shigefumi Ishiguro

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/06 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4082 ,  G11C11/4093

摘要： A semiconductor memory device includes a memory cell array, an output buffer circuit and an input buffer circuit. The memory cell array includes a plurality of memory cells holding data. The output buffer circuit outputs data read from the memory cells. The input buffer circuit receives an address signal for the memory cells and includes a noise filter to remove noise. The filter length of the noise filter is variable according to the output capability of the data in the output buffer circuit.

摘要翻译： 半导体存储器件包括存储单元阵列，输出缓冲电路和输入缓冲电路。 存储单元阵列包括保存数据的多个存储单元。 输出缓冲电路输出从存储单元读出的数据。 输入缓冲电路接收存储单元的地址信号，并且包括用于去除噪声的噪声滤波器。 噪声滤波器的滤波器长度根据输出缓冲电路中数据的输出能力而变化。