公开(公告)号：US09274750B2

公开(公告)日：2016-03-01

申请号：US13452690

申请日：2012-04-20

申请人： Tong Sun ,  Weizhong Chen ,  Zhikun Cheng ,  Yuanbin Guo

发明人： Tong Sun ,  Weizhong Chen ,  Zhikun Cheng ,  Yuanbin Guo

IPC分类号： G06F7/48 ,  G06F7/483 ,  G06F7/544

CPC分类号： G06F7/4806 ,  G06F7/483 ,  G06F7/5443

摘要： An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.

摘要翻译： 提供了一种用于浮点复数乘法的数字计算的方法和相关装置的实施例。 该方法包括接收输入加数，第一产品和第二产品。 输入加法，第一产品和第二产品分别具有尾数和指数。 该方法包括以输入加数，第一乘积和第二乘积的较小指数移动两者的尾数，使其与输入加法器，第一乘积和第二乘积的最大指数的尾数对齐， 并添加对齐的输入加数，对齐的第一个产品和对齐的第二个产品。

公开(公告)号：US20130282778A1

公开(公告)日：2013-10-24

申请号：US13452690

申请日：2012-04-20

申请人： Tong Sun ,  Weizhong Chen ,  Zhikun Cheng ,  Yuanbin Guo

发明人： Tong Sun ,  Weizhong Chen ,  Zhikun Cheng ,  Yuanbin Guo

IPC分类号： G06F7/483 ,  G06F17/10 ,  G06F7/499 ,  G06F5/01

CPC分类号： G06F7/4806 ,  G06F7/483 ,  G06F7/5443

摘要： An embodiment of a method and a related apparatus for digital computation of a floating point complex multiply-add is provided. The method includes receiving an input addend, a first product, and a second product. The input addend, the first product and the second product each respectively has a mantissa and an exponent. The method includes shifting the mantissas of the two with smaller exponents of the input addend, the first product, and the second product to align together with the mantissa of the one with largest exponent of the input addend, the first product and the second product, and adding the aligned input addend, the aligned first product and the aligned second product.

摘要翻译： 提供了一种用于浮点复数乘法的数字计算的方法和相关装置的实施例。 该方法包括接收输入加数，第一产品和第二产品。 输入加法，第一产品和第二产品分别具有尾数和指数。 该方法包括以输入加数，第一乘积和第二乘积的较小指数移动两者的尾数，使其与输入加法器，第一乘积和第二乘积的最大指数的尾数对齐， 并添加对齐的输入加数，对齐的第一个产品和对齐的第二个产品。

公开(公告)号：US20130282777A1

公开(公告)日：2013-10-24

申请号：US13452701

申请日：2012-04-20

申请人： Yuanbin Guo ,  Tong Sun ,  Weizhong Chen

发明人： Yuanbin Guo ,  Tong Sun ,  Weizhong Chen

IPC分类号： G06F7/483 ,  G06F7/499 ,  G06F17/10

CPC分类号： G06F7/483

摘要： An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.

摘要翻译： 用于以混合浮点格式对输入数据进行数值运算的系统和方法的实施例包括将输入数据表示为符号位，指数位和尾数位。 指数位被表示为包括指数偏差的无符号整数，并且带符号数值为零被表示为尾数位和指数位的第一保留组合。 尾数位和指数位的所有其他组合中的每一个表示真实的有限非零数。 尾数位在尾数位和指数位的所有其他组合的小数点之前以“一”位操作。

公开(公告)号：US09792087B2

公开(公告)日：2017-10-17

申请号：US13452701

申请日：2012-04-20

申请人： Yuanbin Guo ,  Tong Sun ,  Weizhong Chen

发明人： Yuanbin Guo ,  Tong Sun ,  Weizhong Chen

IPC分类号： G06F7/483

CPC分类号： G06F7/483

摘要： An embodiment of a system and method for performing a numerical operation on input data in a hybrid floating-point format includes representing input data as a sign bit, exponent bits, and mantissa bits. The exponent bits are represented as an unsigned integer including an exponent bias, and a signed numerical value of zero is represented as a first reserved combination of the mantissa bits and the exponent bits. Each of all other combinations of the mantissa bits and the exponent bits represents a real finite non-zero number. The mantissa bits are operated on with a “one” bit before a radix point for the all other combinations of the mantissa bits and the exponent bits.

公开(公告)号：US07936813B2

公开(公告)日：2011-05-03

申请号：US11895098

申请日：2007-08-23

申请人： Weizhong Chen

发明人： Weizhong Chen

IPC分类号： H03H7/30 ,  H03K5/159 ,  H03D3/00 ,  H04L27/14 ,  H04L1/02 ,  H04B1/10

CPC分类号： H04L27/2003 ,  H04B7/08 ,  H04L25/03133 ,  H04L2025/03477

摘要： Method in a diversity antenna GMSK receiver of determining interference canceling equalizers and corresponding equalizers are described. The method includes providing a plurality of GMSK received signals; de-rotating and splitting each of the plurality of received signals into in phase and quadrature parts to provide a multiplicity of real valued branches; calculating linear equalizers for each of a multiplicity of subsets of the multiplicity of real valued branches; and providing an interference canceling equalizer for each of the multiplicity of real valued branches, each interference canceling equalizer corresponding to a weighted combination of the linear equalizers. A corresponding equalizer includes eight linear equalizers processing four branch signals corresponding to real (I) and quadrature (Q) parts of a GMSK diversity signal from two antennas.

摘要翻译： 描述了确定干扰消除均衡器和对应的均衡器的分集天线GMSK接收机中的方法。 该方法包括提供多个GMSK接收信号; 将所述多个接收信号中的每一个去旋转并分离成相位和正交部分，以提供多个实数值分支; 为多个实值分支的多个子集中的每一个计算线性均衡器; 以及为多个实值分支中的每一个提供干扰消除均衡器，每个干扰消除均衡器对应于线性均衡器的加权组合。 对应的均衡器包括八个线性均衡器，其处理来自两个天线的GMSK分集信号的实数（I）和正交（Q）部分的四个分支信号。

公开(公告)号：US07376207B2

公开(公告)日：2008-05-20

申请号：US09794285

申请日：2001-02-27

申请人： Weizhong Chen

发明人： Weizhong Chen

IPC分类号： H03D3/00

CPC分类号： H04L27/14 ,  H04L25/03178 ,  H04L25/03343 ,  H04L27/2334

摘要： A receiver architecture for receiving an FSK signal having a predetermined number of modulation levels includes a selectivity filter (206) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter bandwidth of about one-half the bandwidth of a pre-modulation filter in a transmitter sending the FSK signal. A discriminator (208) is coupled to the selectivity filter for demodulating the signal. A symbol recovery processor (210) is coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

摘要翻译： 用于接收具有预定数量的调制电平的FSK信号的接收机架构包括选择性滤波器（206），用于选择性地通过所需信道并拒绝不想要的信道。 选择性滤波器在发送FSK信号的发射机中具有约为预调制滤波器带宽的一半的滤波器带宽。 鉴频器（208）耦合到选择滤波器以解调该信号。 符号恢复处理器（210）耦合到鉴别器，用于通过利用每个符号时间的N个状态的最大似然序列估计（MLSE）技术来恢复符号，其中N等于预定数量的调制级，并且其中在 用于符号转换的MLSE被优化，其带宽大大小于预调制滤波器的带宽。

公开(公告)号：US20070274477A1

公开(公告)日：2007-11-29

申请号：US11433590

申请日：2006-05-12

申请人： Weizhong Chen

发明人： Weizhong Chen

IPC分类号： H04M11/00

CPC分类号： H04B7/2675 ,  H04W56/0035 ,  H04W92/10

摘要： A FCCH Burst detector includes a tone detection filter centered at 67.7 KHz, a tone rejection filter centered at −67.7 KHz, moving average power calculation for the two filter outputs, and a detection logic. A FCCH burst is detected when the ratio of the moving average power of the tone detection filter output to that of the tone rejection filter output is larger than a threshold for a period longer than a threshold. The FB tone end time is detected when the ratio falls back to a threshold or the moving average power of the tone detection filter output falls below a threshold of the average power of the tone detection filter output over a predetermined period. The tone detection filter and the tone rejection filter is implemented by first frequency-shifting the received signal by −67.7 KHz and +67.7 KHz in parallel, then passing the two frequency-shifted signals through two separate low-pass filters.

摘要翻译： FCCH突发检测器包括以67.7KHz为中心的色调检测滤波器，以-67.7KHz为中心的色调滤波器，两个滤波器输​​出的移动平均功率计算和检测逻辑。 当音调检测滤波器输出的移动平均功率与音调抑制滤波器输出的移动平均功率的比值大于阈值时，检测到FCCH突发。 当比率下降到阈值或音调检测滤波器输出的移动平均功率在预定时段内降低到音调检测滤波器输出的平均功率的阈值以下时，检测FB音结束时间。 音调检测滤波器和音调抑制滤波器通过首先对接收到的信号进行-67.7KHz和+67.7KHz的并行频移，然后将两个频移信号通过两个单独的低通滤波器来实现。

公开(公告)号：US07266359B2

公开(公告)日：2007-09-04

申请号：US10963387

申请日：2004-10-12

申请人： Weizhong Chen ,  Robert Molina

发明人： Weizhong Chen ,  Robert Molina

IPC分类号： H04B1/10 ,  G06F3/033

CPC分类号： H04B1/30 ,  H04L25/062 ,  H04L25/064 ,  H04L2027/0095

摘要： A method for removing direct current (DC) interference from a signal received by a communication receiver is provided that removes both a DC offset signal induced by the communication receiver and transmitter. The method includes removing the estimated DC offset from the received signal, correcting a frequency shift in the received signal, estimating a second DC offset signal induced by a source of the received signal, such as a transmitter and removing the estimated second DC offset from the received signal. The receiver DC offset signal is estimated and removed prior to performing a timing carrier offset correction using Barker code manipulation to remove receiver-induced DC offset interference and to sum all Barker chips after effectively multiplying Barker codes to correlate to a Barker sequence unaffected by the receiver DC offset signal.

摘要翻译： 提供一种从通信接收机接收的信号中去除直流（DC）干扰的方法，其消除由通信接收机和发射机引起的DC偏移信号。 该方法包括从接收到的信号中去除估计的DC偏移，校正接收信号中的频移，估计由诸如发射机的接收信号的源引起的第二DC偏移信号，并从第 接收信号。 在使用Barker码操作执行定时载波偏移校正之前估计和去除接收机DC偏移信号，以消除接收机引起的DC偏移干扰，并且在有效地将Barker码相乘以与接收机不受影响的Barker序列相关之后求和所有Barker码片 直流偏移信号。

公开(公告)号：US20050111530A1

公开(公告)日：2005-05-26

申请号：US10721950

申请日：2003-11-25

申请人： Weizhong Chen ,  Sekchin Chang ,  Satish Kulkarni

发明人： Weizhong Chen ,  Sekchin Chang ,  Satish Kulkarni

IPC分类号： H04B1/707 ,  H04L7/04 ,  H04L27/00 ,  H04L27/26

CPC分类号： H04L27/2657 ,  H04B2201/70701 ,  H04L7/042 ,  H04L27/2613 ,  H04L27/2662 ,  H04L27/2675 ,  H04L2027/0046

摘要： A timing and carrier error detector module (127) of a communication receiver (111). The timing and carrier error detector module uses phase information of a correlated signal (e.g. a Barker de-spread signal) to generate a timing signal and carrier error signal. In one example, the phase information includes a phase error signal of the correlated signal. In one example, the timing and carrier error detector module calculates an indication of the variance of the phase error signal for a plurality of sample positions over a plurality of Barker symbol intervals. The timing signal is based upon the sample position having a minimum indication of a variance.

摘要翻译： 通信接收机（111）的定时和载波误差检测器模块（127）。 定时和载波误差检测器模块使用相关信号（例如巴克解扩信号）的相位信息来产生定时信号和载波误差信号。 在一个示例中，相位信息包括相关信号的相位误差信号。 在一个示例中，定时和载波误差检测器模块在多个巴克符号间隔上计算多个采样位置的相位误差信号的方差的指示。 定时信号基于具有方差的最小指示的采样位置。

公开(公告)号：US06836520B1

公开(公告)日：2004-12-28

申请号：US09709727

申请日：2000-11-10

申请人： Weizhong Chen ,  Leo Dehner

发明人： Weizhong Chen ,  Leo Dehner

IPC分类号： H04L700

CPC分类号： H04L27/0012 ,  H04L7/042 ,  H04L7/06 ,  H04L2027/0034

摘要： A synchronization signal includes a plurality of predetermined synchronization symbols shaped by a predetermined symbol pulse. A receiver (100) receives (202) a signal including the synchronization signal, and a processor (106)determines (204) a first plurality of cross-correlations between the predetermined symbol pulse and the received signal. The processor calculates (206) a plurality of sums of products of the plurality of predetermined synchronization symbols and a predetermined subset of the first plurality of cross-correlations. The plurality of sums are mathematically equivalent to a second plurality of cross-correlations between the synchronization signal and the received signal. The processor locates (208) a peak of the plurality of sums to establish receiver synchronization.

摘要翻译： 同步信号包括由预定符号脉冲整形的多个预定同步符号。 接收器（100）接收（202）包括同步信号的信号，并且处理器（106）确定（204）预定符号脉冲与接收信号之间的第一多个互相关。 处理器计算（206）多个预定同步符号的乘积和与第一多个互相关的预定子集的多个和。 多个和在数学上等同于同步信号和接收信号之间的第二多个互相关。 处理器定位（208）多个和的峰值以建立接收机同步。