公开(公告)号：US5835969A

公开(公告)日：1998-11-10

申请号：US517271

申请日：1995-08-22

申请人： Toru Inagaki ,  Kenichi Fujisaki

发明人： Toru Inagaki ,  Kenichi Fujisaki

IPC分类号： G01R31/3183 ,  G01R31/3181 ,  G01R31/319 ,  G06F9/34 ,  G06F12/00 ,  G06F12/02 ,  G11C29/04 ,  G11C29/10 ,  G11C29/18 ,  G11C29/20 ,  G06F9/26 ,  G06F12/10

CPC分类号： G06F9/34 ,  G01R31/31813 ,  G11C29/18 ,  G11C29/20 ,  G01R31/31921

摘要： An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a semiconductor device under test during a test process in real time and generates column addresses for the device under test by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, Z address signal, and an operation mode control signal is arranged, a conversion memory that outputs certain conversion table contents is arranged, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with the burst length control signal. In another aspect, the address pattern generator includes a counter that loads the lower address signal from the Y address generator section for the sequential mode and loads a fixed value for the interleave mode, an exclusive OR gate that provides an output signal of the counter to an input terminal and the lower address signal from the Y address generation section to the other input terminal, and a multiplexer that selects the output signal of the counter for the sequential mode and the output signal of the exclusive OR gate for the interleave mode.

摘要翻译： 公开了一种用于测试半导体器件，特别是同步DRAM的地址模式发生器。 地址模式发生器可以在测试过程中实时地切换待测半导体器件的交错模式和顺序模式的地址生成，并且由Y地址生成部分单独生成被测器件的列地址。 地址生成器包括：地址选择器，其从较低的Y地址信号Z地址信号中选择和输出，并且布置有操作模式控制信号;布置输出特定转换表内容的转换存储器;选择并输出 根据突发长度控制信号从转换存储器输出下Y位地址信号。 在另一方面，地址模式发生器包括一个计数器，用于为顺序模式加载来自Y地址生成器部分的较低地址信号，并为交错模式加载固定值，异或门将计数器的输出信号提供给 输入端子和从Y地址产生部分到另一个输入端子的低地址信号，以及多路复用器，用于选择顺序模式的计数器的输出信号和用于交织模式的异或门的输出信号。

公开(公告)号：US5940875A

公开(公告)日：1999-08-17

申请号：US016710

申请日：1998-01-30

申请人： Toru Inagaki ,  Kenichi Fujisaki

发明人： Toru Inagaki ,  Kenichi Fujisaki

IPC分类号： G01R31/3183 ,  G01R31/3181 ,  G01R31/319 ,  G06F9/34 ,  G06F12/00 ,  G06F12/02 ,  G11C29/04 ,  G11C29/10 ,  G11C29/18 ,  G11C29/20 ,  G01K31/28

CPC分类号： G06F9/34 ,  G01R31/31813 ,  G11C29/18 ,  G11C29/20 ,  G01R31/31921

摘要： An address pattern generator for testing a semiconductor device, particularly, a synchronous DRAM (SDRAM) is disclosed. The address pattern generator can switch an interleave mode and a sequential mode of address generation for a SDRAM during a test process in real time and generates column addresses for the SDRAM by a Y address generation section alone. The address generator includes an address selector that selects and outputs from a lower Y address signal, a Z address signal, and an operation mode control signal, a conversion memory that outputs data based on a conversion table, a multiplexer that selects and outputs an output from the conversion memory and the lower Y address signal in accordance with a burst length control signal. In another aspect, the address pattern generator includes a counter that loads the lower address signal from the Y address generator section for the sequential mode while a fixed value for the interleave mode, an exclusive OR gate that receives an output signal of the counter to an input terminal and the lower address signal from the Y address generation section to the other input terminal, and a multiplexer that selects the output signal of the counter for the sequential mode and the output signal of the exclusive OR gate for the interleave mode.

摘要翻译： 公开了一种用于测试半导体器件，特别是同步DRAM（SDRAM）的地址模式发生器。 地址模式发生器可以在测试过程中实时地切换SDRAM的交错模式和顺序地址生成模式，并且由Y地址生成部分单独生成用于SDRAM的列地址。 地址生成器包括：地址选择器，其从较低的Y地址信号，Z地址信号和操作模式控制信号中选择和输出，转换存储器，其基于转换表输出数据;多路复用器，其选择和输出输出 根据突发长度控制信号从转换存储器和较低的Y地址信号。 在另一方面，地址模式发生器包括一个计数器，用于为顺序模式加载来自Y地址生成器部分的较低地址信号，而交织模式的固定值，接收该计数器的输出信号的异或门 输入端子和从Y地址产生部分到另一个输入端子的较低地址信号，以及多路复用器，用于选择用于顺序模式的计数器的输出信号和用于交错模式的异或门的输出信号。

公开(公告)号：US07636877B2

公开(公告)日：2009-12-22

申请号：US11774615

申请日：2007-07-09

申请人： Kenichi Fujisaki

发明人： Kenichi Fujisaki

IPC分类号： G01R31/28

CPC分类号： G11C29/56004 ,  G01R31/31917 ,  G11C29/56 ,  G11C29/56008 ,  G11C2029/5606

摘要： The test apparatus includes: a pattern memory that stores therein data to be outputted to the device under test; a device judgment section that judges whether the device under test passes or fails based on an output signal; the number of data information storage section that stores therein the number of data information based on the number of logic H data included in an input data; a counter that receives output data outputted from the pattern memory to the device under test and counts the number of logic H data included in the output data; a pattern memory judgment section that judges that the data stored in the pattern memory is correct when the number of data information on the input data is corresponding to the number of logic H data counted by the counter and outputs a signal according to this judgment result.

摘要翻译： 测试装置包括：存储要输出到被测设备的数据的模式存储器; 设备判断部，其基于输出信号判断被测设备是否通过或失败; 存储在输入数据中包含的逻辑H数据的数量的数据信息数的数据信息存储部的数量; 将从图案存储器输出的输出数据接收到被测设备的计数器，并对包含在输出数据中的逻辑H数据进行计数; 当输入数据的数据信息的数量对应于由计数器计数的逻辑H数据的数量时，判定存储在图案存储器中的数据正确的模式存储器判断部分，并根据该判断结果输出信号。

公开(公告)号：US6006349A

公开(公告)日：1999-12-21

申请号：US809632

申请日：1997-03-26

申请人： Kenichi Fujisaki

发明人： Kenichi Fujisaki

IPC分类号： G01R31/3181 ,  G06F11/27 ,  G01R31/28

CPC分类号： G01R31/31813 ,  G06F11/27

摘要： A high speed pattern generating method by which a pattern signal having a speed higher than conventional speed can be generated using a sequence control part operating at a speed equivalent to a conventional speed and a high speed pattern generator for materializing the method are provided. A high speed pattern signal having a speed multiple of the number of multiplexing against an operation speed of the sequence control part is generated by generating multi-phase sub patterns from a plurality of sub pattern generating parts and by taking out for multiplexing the multi-phase sub patterns one phase by one phase by a multiplexing circuit. Further, an instruction memory of a pattern generator is uniquely arranged to materialize the high speed pattern generating method.

摘要翻译： PCT No.PCT / JP96 / 02104 Sec。 371日期1997年3月26日 102（e）1997年3月26日PCT PCT 1996年7月26日PCT公布。 第WO97 / 05499号公报 日期1997年2月13日利用以与传统速度相当的速度运行的顺序控制部分和用于实现该方法的高速图案发生器可以产生具有比常规速度更高的速度的图形信号的高速模式生成方法 被提供。 通过从多个子图形生成部生成多相子图案，并通过取出复用多相的多相图来生成具有针对序列控制部的运算速度的复用次数的倍数的高速模式信号 子模式通过复用电路一相一相。 此外，图案发生器的指令存储器被唯一地排列以实现高速模式生成方法。

公开(公告)号：US08261139B2

公开(公告)日：2012-09-04

申请号：US12709389

申请日：2010-02-19

申请人： Kenichi Fujisaki

发明人： Kenichi Fujisaki

IPC分类号： G11C29/00

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C2029/5606

摘要： A test apparatus includes a fail memory (AFM) for storing therein fail information in association with each of the addresses of a memory under test and a mark memory (CMM) for storing therein, in association with each of the addresses of the memory under test, validity information indicating whether the fail information stored in the AFM is valid. When the validity information read from the CMM in association with an address under test indicates that the fail information that has been stored in the AFM is invalid, the test apparatus overwrites the fail information stored in the AFM with the fail information that is newly generated by a current test. On the other hand, when the validity information read from the CMM indicates that the fail information is valid, the test apparatus updates the fail information stored in the AFM with the new fail information and writes the updated fail information back into the AFM. When overwriting the fail information that has been stored in the AFM with the new fail information, the test apparatus writes into the CMM the validity information that indicates that the new fail information is valid. Initialization of the AFM is performed in such a manner that, before and after the initialization, different validity information indicates validity of the fail information.

摘要翻译： 一种测试设备包括：故障存储器（AFM），用于存储与被测存储器的每个地址相关联的故障信息和用于存储在其中的标记存储器（CMM），与被测存储器的每个地址相关联 指示存储在AFM中的故障信息是否有效的有效性信息。 当与被测地址相关联地从CMM读取的有效性信息指示存储在AFM中的故障信息无效时，测试装置用AFM新生成的故障信息覆盖存储在AFM中的故障信息， 目前的考试。 另一方面，当从CMM读取的有效性信息指示故障信息有效时，测试装置利用新的故障信息更新存储在AFM中的故障信息，并将更新的故障信息写入AFM。 当使用新的故障信息覆盖存储在AFM中的故障信息时，测试设备向CMM写入指示新的故障信息有效的有效性信息。 执行AFM的初始化，使得在初始化之前和之后，不同的有效性信息指示故障信息的有效性。

公开(公告)号：US5481671A

公开(公告)日：1996-01-02

申请号：US122490

申请日：1993-12-30

申请人： Kenichi Fujisaki

发明人： Kenichi Fujisaki

IPC分类号： G11C29/00 ,  G11C29/20 ,  G11C29/44 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C29/56 ,  G11C29/003 ,  G11C29/20 ,  G11C29/44 ,  G11C8/16

摘要： A failure analysis memory (7) having main and sub failure analysis memories (7a, 7b) has two counters (C1, C2), a multiplexer (MUX), two registers (RG1, RG2)and a comparator 14. A value corresponding to the size of a column address of a memory under test (2) is set in the register (RG1) and a stop address is set in the register (RG2). Each time a SAM part (2b) of the memory under test sequentially outputs data in an address area specified by a transfer row address and a start address, one of the counters is incremented on a one-by-one basis from a start address set therein, and its count value is selected by the multiplexer (MUX) and output as a sub address signal (SA'). During this time, the other counter in the non-counting state loads therein a main address specifying data that a RAM part 2a transfers next. When the memory under test operates in a simple read/transfer mode or a split read/transfer mode, a column address in the output from the multiplexer (MUX) is compared by the comparator (14) with the value set in the register (RG1). When the memory under test operates in a stop control split read/transfer mode the column address is compared with the value set in the register (RG2). When coincidence is detected by the comparator (14), a controller (12) switches the counting and non-counting states of the counters (C1, C2).

摘要翻译： PCT No.PCT / JP93 / 00118 Sec。 371日期：1993年12月30日 102（e）日期1993年12月30日PCT提交1993年2月2日PCT公布。 公开号WO93 / 15462 具有主故障分析存储器（7a，7b）的故障分析存储器（7）具有两个计数器（C1，C2），多路复用器（MUX），两个寄存器（RG1，RG2）和 对应于被测存储器（2）的列地址的大小的值被设置在寄存器（RG1）中，并且在寄存器（RG2）中设置停止地址。 每次测试的存储器的SAM部分（2b）顺序地输出由传送行地址和起始地址指定的地址区域中的数据时，其中一个计数器从起始地址集逐个递增 并且其计数值由多路复用器（MUX）选择，并作为子地址信号（SA'）输出。 在此期间，非计数状态下的另一个计数器在其中装载下一个RAM部分2a转移的主地址指定数据。 当被测存储器以简单的读取/传送模式或分离读取/传送模式工作时，来自多路复用器（MUX）的输出中的列地址被比较器（14）与在寄存器（RG1）中设置的值进行比较 ）。 当被测存储器以停止控制分离读/写模式运行时，将列地址与寄存器（RG2）中设置的值进行比较。 当比较器（14）检测到符合时，控制器（12）切换计数器（C1，C2）的计数和非计数状态。

公开(公告)号：US4958345A

公开(公告)日：1990-09-18

申请号：US287139

申请日：1988-12-21

申请人： Kenichi Fujisaki

发明人： Kenichi Fujisaki

IPC分类号： G11C29/00 ,  G11C29/02 ,  G11C29/44 ,  G11C29/56

CPC分类号： G11C29/56

摘要： In a memory testing device for testing a memory capable of effecting a write and a read in pixel, plane and block modes, there are provided a pattern generator for generating an address and data for supply to the memory under test and a buffer memory which has memory chips equal in number to the square of the number of bits of the data. The same data as that to be written in the memory under test is written in the buffer memory in the same mode as in the memory under test, and the data is read out in the same mode as in the memory under test. The data thus read out of the buffer memory is used as expected value data for logical comparison with data read out of the memory under test.

公开(公告)号：US08677197B2

公开(公告)日：2014-03-18

申请号：US13338243

申请日：2011-12-28

申请人： Kenichi Fujisaki

发明人： Kenichi Fujisaki

IPC分类号： G11C29/00

CPC分类号： G11C29/56008 ,  G11C2029/5606

摘要： A test apparatus including a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section.

摘要翻译： 一种测试装置，包括：第一缓冲器部分和第二缓冲器部件，每个缓冲器都失败数据和地址数据; 地址失败存储器部分，其使用RMW进程将缓冲在第一缓冲器部分中的故障数据写入由与故障数据相对应的地址数据指示的内部存储器的地址; 以及控制部，其中当所述第一缓冲器部分的未使用容量变得小于或等于预定的第一阈值时，在从所述测试部分输出的故障数据和地址数据被提供给所述第一缓冲器部分的状态下， 将从测试部分输出的故障数据和地址数据提供给第二缓冲器部分，而不是提供给第一缓冲器部分。

公开(公告)号：US08325547B2

公开(公告)日：2012-12-04

申请号：US13298207

申请日：2011-11-16

申请人： Kenichi Fujisaki

发明人： Kenichi Fujisaki

IPC分类号： G11C29/00

CPC分类号： G11C29/56 ,  G11C29/56008

摘要： A test apparatus that tests a memory under test, comprising an address fail memory that stores address fail data for each address; a block fail memory that stores block fail data for each block; a reading section that reads the address fail data from the address fail memory for each block; a row fail counter that, for each row address in a group including a plurality of the blocks in the memory under test, counts the fail cells indicated by the address fail data; and a column fail counter that counts the fails cells for each column address.

摘要翻译： 一种测试被测存储的测试装置，包括存储每个地址的地址故障数据的地址故障存储器; 一个块失效存储器，用于存储每个块的块失败数据; 读取部分，从每个块的地址失败存储器读取地址失败数据; 行故障计数器，对于包括被测存储器中的多个块的组中的每个行地址，对由地址失败数据指示的故障单元进行计数; 以及一个列失败计数器，用于计算每个列地址的故障单元。

公开(公告)号：US6032281A

公开(公告)日：2000-02-29

申请号：US175715

申请日：1998-10-20

申请人： Kenichi Fujisaki

发明人： Kenichi Fujisaki

IPC分类号： G01R31/3181 ,  G01R31/319 ,  G01R31/3193 ,  G11C29/36 ,  G11C29/56 ,  G01R31/28

CPC分类号： G11C29/36 ,  G01R31/31813 ,  G01R31/31919 ,  G01R31/31928 ,  G11C29/56 ,  G01R31/3193

摘要： A test pattern generator for performing a block write function testing at high speed. The test pattern generator includes a data register which takes in data signal from a data generator by a first write signal from a control signal generator, an address selector which takes in specific bits from an address generated by an address generator, a mask data register file which takes the data signal in an area specified by a second write signal from the control signal generator, a write data register file which takes the data signal in an area specified by a third write signal from the control signal generator, and data formatter which outputs either an output data of the data register or of the data generator based on the above signals.

摘要翻译： 用于高速执行块写功能测试的测试码发生器。 测试模式发生器包括数据寄存器，该数据寄存器通过来自控制信号发生器的第一写入信号从数据发生器接收数据信号，地址选择器从地址发生器产生的地址中接收特定位，掩码数据寄存器文件 其将数据信号从来自控制信号发生器的第二写入信号指定的区域中，将数据信号从由控制信号发生器输出的第三写入信号指定的区域中的写数据寄存器文件和输出的数据格式化器 基于上述信号的数据寄存器或数据发生器的输出数据。