公开(公告)号：US10261857B2

公开(公告)日：2019-04-16

申请号：US15449383

申请日：2017-03-03

申请人： Toshiba Memory Corporation

发明人： Katsuhiko Ueki ,  Sumio Kuroda ,  Yasuyuki Ozawa

IPC分类号： G06F11/10 ,  G06F11/07 ,  G11C16/26 ,  G11C16/34 ,  H03M13/11 ,  H03M13/00

摘要： A memory system includes a memory that includes a plurality of memory cells, and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.

公开(公告)号：US10789125B2

公开(公告)日：2020-09-29

申请号：US16380003

申请日：2019-04-10

申请人： Toshiba Memory Corporation

发明人： Katsuhiko Ueki ,  Sumio Kuroda ,  Yasuyuki Ozawa

IPC分类号： G06F11/10 ,  G11C7/10 ,  G11C16/10 ,  H03M13/35 ,  G06F11/07 ,  G11C16/26 ,  G11C16/34 ,  H03M13/11 ,  H03M13/00

摘要： A memory system includes a plurality of memory cells and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.

公开(公告)号：US09940192B2

公开(公告)日：2018-04-10

申请号：US14528825

申请日：2014-10-30

申请人： Toshiba Memory Corporation

发明人： Fubito Igari ,  Hiroyuki Suto ,  Yasuyuki Ozawa

IPC分类号： G11C29/00 ,  G06F11/10 ,  G11C7/04 ,  G06F3/06 ,  G11C29/04

CPC分类号： G06F11/1008 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1048 ,  G11C7/04 ,  G11C2029/0411

摘要： According to one embodiment, a non-volatile semiconductor storage apparatus is configured to decide determination periods respectively corresponding to each of management blocks based on rewrite count information items and a temperature, and to perform a determination processing for each of management blocks for each determination period. The determination processing includes determining whether first data read from a block in the blocks is normal based on the number of errors that are occurred in the first data. The apparatus is configured to perform a rewrite processing of rewriting the first data to second data which is error-corrected when it is determined that the first data is not normal.

公开(公告)号：US09788463B2

公开(公告)日：2017-10-10

申请号：US14842313

申请日：2015-09-01

申请人： Toshiba Memory Corporation

发明人： Yasuyuki Ozawa ,  Fuminori Kimura ,  Masaaki Niijima ,  Masahiro Iijima ,  Yoshiharu Matsuda ,  Kenichi Sawanaka ,  Kazuhiro Yoshida

IPC分类号： H05K7/20

CPC分类号： H05K7/20754

摘要： A semiconductor memory device includes a semiconductor memory unit, a memory controller, a cover unit having a first portion covering the semiconductor memory unit and a second portion covering the memory controller, a first heat conduction member disposed between the semiconductor memory unit and the first portion of the cover unit, and a second heat conduction member disposed between the memory controller and the second portion of the cover. The cover unit has a gap formed between the first and second portions.