公开(公告)号：US07503017B2

公开(公告)日：2009-03-10

申请号：US10963730

申请日：2004-10-14

申请人： Toshikatsu Hosono ,  Katsuhito Hashiba

发明人： Toshikatsu Hosono ,  Katsuhito Hashiba

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： A library generation device determines a characteristic approximation function based on a characteristic extraction table to calculate characteristic data corresponding to a client's conditions in accordance with the characteristic approximation function. A library for verification including the calculated characteristic data and format information of a reference library is generated in the same format as the reference library.

摘要翻译： 库生成装置基于特征提取表确定特征近似函数，以根据特征近似函数计算与客户条件对应的特征数据。 用于验证的库包括计算的参考库的特征数据和格式信息以与参考库相同的格式生成。

公开(公告)号：US20050266495A1

公开(公告)日：2005-12-01

申请号：US10963730

申请日：2004-10-14

申请人： Toshikatsu Hosono ,  Katsuhito Hashiba

发明人： Toshikatsu Hosono ,  Katsuhito Hashiba

IPC分类号： G06F17/50 ,  G01N33/48 ,  G01N33/50 ,  G01N33/53 ,  H01L21/82 ,  G06F19/00

CPC分类号： G06F17/5022

摘要： A library generation device determines a characteristic approximation function based on a characteristic extraction table to calculate characteristic data corresponding to a client's conditions in accordance with the characteristic approximation function. A library for verification including the calculated characteristic data and format information of a reference library is generated in the same format as the reference library.

摘要翻译： 库生成装置基于特征提取表确定特征近似函数，以根据特征近似函数计算与客户条件对应的特征数据。 用于验证的库包括计算的参考库的特征数据和格式信息以与参考库相同的格式生成。

公开(公告)号：US20080034338A1

公开(公告)日：2008-02-07

申请号：US11878264

申请日：2007-07-23

申请人： Toshikatsu Hosono

发明人： Toshikatsu Hosono

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A timing analysis device for preventing the amount of data and the number of analysis operations from increasing in a statistical analysis, while improving the timing convergence in a path included in a net under relatively strict timing conditions. The timing analysis device performs a static timing analysis to extract a net under relatively strict timing conditions from the analysis result and generate a timing list. The device further performs delay distribution calculation for the extracted net to analyze the delay variation in each of one or more instances included in the net. The device retrieves the timing list and sets a unique delay variation for each instance to calculate a delay distribution. The device further performs a statistical timing analysis based on the calculated delay distribution.

摘要翻译： 一种用于在统计分析中防止数据量和分析操作数量增加的定时分析装置，同时在相对严格的定时条件下改善包括在网络中的路径中的定时收敛。 定时分析装置执行静态时序分析，从分析结果在相对严格的时序条件下提取网络，并生成定时列表。 该装置还对所提取的网进行延迟分布计算，以分析网中包括的一个或多个实例中的每一个中的延迟变化。 设备检索定时列表，并为每个实例设置唯一的延迟变化，以计算延迟分布。 该装置还基于所计算的延迟分布进行统计时序分析。

公开(公告)号：US20060109032A1

公开(公告)日：2006-05-25

申请号：US11080555

申请日：2005-03-16

申请人： Toshikatsu Hosono

发明人： Toshikatsu Hosono

IPC分类号： H03D13/00

CPC分类号： G01R29/023 ,  G01R31/3016 ,  G01R31/31725

摘要： A timing verification apparatus calculates a pulse width variation coefficient based on a pulse width of an input clock signal, a delay value of the clock signal, and an operation frequency. The apparatus then calculates the pulse width for a delayed clock signal provided to a clock input terminal of a flip flop (FF) using the pulse width variation coefficient. Further, the apparatus compares the calculated pulse width with a standard value. The timing verification apparatus calculates the pulse width of the delayed clock signal provided to the clock input terminal of the FF using the pulse width of the clock signal, and a rise delay and a fall delay of the path. The apparatus considers on-chip variations and accurately executes timing verification for signals.

摘要翻译： 定时验证装置基于输入时钟信号的脉冲宽度，时钟信号的延迟值和操作频率来计算脉宽变化系数。 然后，该装置使用脉冲宽度变化系数来计算提供给触发器（FF）的时钟输入端的延迟时钟信号的脉冲宽度。 此外，该装置将所计算的脉冲宽度与标准值进行比较。 定时验证装置使用时钟信号的脉冲宽度和路径的上升延迟和下降延迟来计算提供给FF的时钟输入端的延迟时钟信号的脉冲宽度。 该装置考虑片上变化并准确地执行信号的定时验证。

公开(公告)号：US07562266B2

公开(公告)日：2009-07-14

申请号：US11389008

申请日：2006-03-27

申请人： Toshikatsu Hosono

发明人： Toshikatsu Hosono

IPC分类号： G11B20/20 ,  G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31708

摘要： A timing verification device for performing effective timing verification while correctly taking variation into account. The timing verification device receives a technology file and extracts a coefficient of variation for each cell based on conditions of the manufacturing process of a semiconductor integrated circuit. The timing verification device receives a timing list and computes the variation amounts corresponding to the rise and fall of a clock signal or a correction coefficient obtained by taking into account the correlation between the rise and the fall based on the extracted coefficients of variation. The timing verification device re-computes a delay time using the amount of variation or the correction coefficient and determines the pulse width and the timing based on the recomputed delay time to output the determination result as a timing report.

摘要翻译： 一种定时验证装置，用于在正确考虑变化的同时进行有效的定时验证。 定时验证装置根据半导体集成电路的制造过程的条件接收技术文件并提取每个小区的变异系数。 定时验证装置接收定时列表，并根据所提取的变异系数，计算对应于时钟信号的上升和下降的变化量或通过考虑上升和下降之间的相关性而获得的校正系数。 定时验证装置使用变化量或校正系数重新计算延迟时间，并且基于重新计算的延迟时间确定脉冲宽度和定时，以将确定结果作为定时报告输出。

公开(公告)号：US07299438B2

公开(公告)日：2007-11-20

申请号：US11080555

申请日：2005-03-16

申请人： Toshikatsu Hosono

发明人： Toshikatsu Hosono

IPC分类号： G06F17/50

CPC分类号： G01R29/023 ,  G01R31/3016 ,  G01R31/31725

摘要： A timing verification apparatus calculates a pulse width variation coefficient based on a pulse width of an input clock signal, a delay value of the clock signal, and an operation frequency. The apparatus then calculates the pulse width for a delayed clock signal provided to a clock input terminal of a flip flop (FF) using the pulse width variation coefficient. Further, the apparatus compares the calculated pulse width with a standard value. The timing verification apparatus calculates the pulse width of the delayed clock signal provided to the clock input terminal of the FF using the pulse width of the clock signal, and a rise delay and a fall delay of the path. The apparatus considers on-chip variations and accurately executes timing verification for signals.

摘要翻译： 定时验证装置基于输入时钟信号的脉冲宽度，时钟信号的延迟值和操作频率来计算脉宽变化系数。 然后，该装置使用脉冲宽度变化系数来计算提供给触发器（FF）的时钟输入端的延迟时钟信号的脉冲宽度。 此外，该装置将所计算的脉冲宽度与标准值进行比较。 定时验证装置使用时钟信号的脉冲宽度和路径的上升延迟和下降延迟来计算提供给FF的时钟输入端的延迟时钟信号的脉冲宽度。 该装置考虑片上变化并准确地执行信号的定时验证。

公开(公告)号：US07219320B2

公开(公告)日：2007-05-15

申请号：US10807286

申请日：2004-03-24

申请人： Tetsuo Kawano ,  Satoru Yoshikawa ,  Toshikatsu Hosono ,  Shigenori Ichinose ,  Takashi Yoneda

发明人： Tetsuo Kawano ,  Satoru Yoshikawa ,  Toshikatsu Hosono ,  Shigenori Ichinose ,  Takashi Yoneda

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.

摘要翻译： 根据栅极级的数量，在系数运算单元中计算作为分析对象的路径中的OCV系数，通过根据目标路径中的门级的数量消除每个门的延迟的变化，以及定时分析 通过使用考虑了门级数的OCV系数在定时分析单元中执行目标路径的变化，从而根据目标路径中的门级数减少整个路径的变化程度，从而使 考虑到半导体集成电路的芯片的变化，可以进行准确的时序分析。

公开(公告)号：US20060225014A1

公开(公告)日：2006-10-05

申请号：US11206814

申请日：2005-08-19

申请人： Toshikatsu Hosono

发明人： Toshikatsu Hosono

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： This invention intends to provide timing analysis methods, timing analysis programs, and timing analysis tools for the purpose of performing timing verification in optimum conditions without any excessive variations by statistically dealing with variations in elemental devices forming a semiconductor integrated circuit. In order to verify a timing between two signals, a delay value of a signal propagating through a signal path selected as a candidate for timing analysis is obtained, and with respect to a random variation amount of the delay value, a random variation amount corresponding to the number of gate circuit stages forming the signal path is obtained. Then, based on the delay value and the random variation amount, a most severe variation amount between the two signals in a most severe operating condition is obtained, and based on the most severe variation amount, a respective individual variation coefficient is allocated for each gate circuit, thereby performing a timing analysis.

摘要翻译： 本发明旨在提供定时分析方法，时序分析程序和时序分析工具，以便在最佳条件下执行定时验证，而不会通过统计地处理形成半导体集成电路的元件的变化而产生任何过度的变化。 为了验证两个信号之间的定时，获得通过选择作为定时分析候选的信号路径传播的信号的延迟值，并且对于延迟值的随机变化量，对应于 获得形成信号路径的门电路级数。 然后，基于延迟值和随机变化量，获得在最严重的运行状态下的两个信号之间最严重的变化量，并且基于最严重的变化量，为每个门分配各自的变化系数 电路，从而进行定时分析。

公开(公告)号：US07984406B2

公开(公告)日：2011-07-19

申请号：US12010202

申请日：2008-01-22

申请人： Takeichirou Akamine ,  Toshikatsu Hosono

发明人： Takeichirou Akamine ,  Toshikatsu Hosono

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G01R31/3016

摘要： A computer-implemented timing verification method for obtaining delay time for a signal propagated through a signal path and performing timing verification. The method stores a table including a wiring resistance variation amount and a wiring capacitance variation amount that are in accordance with a geometry deviation of a wire from a reference geometry, extracts a wiring structure of the signal path from a storage unit, extracts a wiring resistance variation amount and a wiring capacitance variation amount that correspond to the extracted wiring structure from the table, generates an on-chip-variation coefficient from the extracted wiring resistance variation amount and wiring capacitance variation amount, and calculates delay time for the signal propagated through the signal path based on the generated on-chip-variation coefficient.

摘要翻译： 一种计算机实现的定时验证方法，用于获得通过信号路径传播的信号的延迟时间并执行定时验证。 该方法存储包括根据线的几何偏差与参考几何相关的布线电阻变化量和布线电容变化量的表，从存储单元提取信号路径的布线结构，提取布线电阻 从表中提取的布线结构对应的变化量和布线电容变化量根据所提取的布线电阻变化量和布线电容变化量生成片上变化系数，并且计算通过 基于生成的片上变化系数的信号路径。

公开(公告)号：US20070266357A1

公开(公告)日：2007-11-15

申请号：US11798338

申请日：2007-05-11

申请人： Atsushi Kimata ,  Toshikatsu Hosono

发明人： Atsushi Kimata ,  Toshikatsu Hosono

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A signal timing analysis method for analyzing timing of a signal propagated along a path including instances. The method includes performing a delay calculation, generating files storing delay information, input slew rate, and output capacitance, performing static timing analysis (STA) based on the delay information, and generating an analysis result. The method includes calculating a delay distribution based on the input slew rate and output capacitance, a probability distribution of a delay time, a probability distribution of a transition time, and a correlation between the delay time and the transition time. The calculation of the delay distribution includes inputting an input slew rate distribution taking into consideration a correlation between output delay and transition distributions for the instance in a preceding stage. The method includes performing STA on the signal propagated along the path based on the analysis result of the STA and delay distribution.

摘要翻译： 一种用于分析沿着包括实例的路径传播的信号的定时的信号定时分析方法。 该方法包括执行延迟计算，产生存储延迟信息的文件，输入转换速率和输出电容，基于延迟信息执行静态时序分析（STA），以及生成分析结果。 该方法包括基于输入转换速率和输出电容，延迟时间的概率分布，转换时间的概率分布以及延迟时间与转换时间之间的相关性来计算延迟分布。 延迟分布的计算包括考虑前一阶段中的实例的输出延迟和转换分布之间的相关性来输入输入转换速率分布。 该方法包括基于STA的分析结果和延迟分布，沿着路径传播的信号执行STA。