-
公开(公告)号：US20240361371A1
公开(公告)日：2024-10-31
申请号：US18767283
申请日：2024-07-09
CPC分类号： G01R29/023 , G01R25/005 , H03K3/037 , H03K5/00 , H03K19/21 , H03K2005/00058
摘要： Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.
-
2.发明授权公开(公告)号：US11982698B2
公开(公告)日：2024-05-14
申请号：US17128825
申请日：2020-12-21
发明人： Masoud Farshchian
IPC分类号： G01S7/28 , G01R29/02 , G01R29/033 , G01S5/02 , G01S7/36 , G01S13/02 , G01S13/76 , G01R29/027 , G06F17/14 , G06F17/16
CPC分类号： G01R29/023 , G01R29/033 , G01S5/0278 , G01S7/36 , G01R29/027 , G01S13/762 , G06F17/14 , G06F17/16
摘要： A feature detection system, the system comprising: at least one processor in operative communication with a signal source, said processor further comprising at least one non-transitory storage medium, wherein at least one non-transitory storage medium contains instructions configured to cause the processor to: apply a joint group sparse denoising and delay estimation approach to a signal received from said signal source; and output statistics regarding the signal, wherein the joint group sparse denoising and delay estimation approach comprises; using the following equation:
{
x
*
,
τ
*
}
=
argmin
x
,
τ
{
1
2
∑
j
=
1
M
y
j
-
x
2
2
+
∑
i
=
0
N
λ
i
φ
i
(
D
i
l
i
x
)
}
where: ϕi are regularization functions; ∥y−x∥22 is a data-fidelity term and, in embodiments, is chosen as the least-square term; li are real numbers; Di are operators, which may be linear filters that can be written in matrix form; λi are regularization parameters; and x*,τ* represent estimates of at least one transmitted pulse and associated delay, and solving the equation for multiple values of ϵ; choosing a vector, x, such that a cost function comprising the data fidelity term and regularization function is minimized; determining the ϵ that corresponds to the x that minimizes the cost function; and calculating the pulse width of the received signal, which corresponds to the desired estimate of the vector, x.-
3.发明公开公开(公告)号：US20240142505A1
公开(公告)日：2024-05-02
申请号：US18274975
申请日：2022-01-12
发明人： Huan Fu , Vincent Leonhardt , Eduard Enderle
CPC分类号： G01R29/0273 , G01R23/09 , G01R29/023 , G01R31/006 , G01R31/34 , H02P27/085
摘要： A method is provided for testing switch signals of an inverter of an electric machine of a drive system of a motor vehicle. The electric machine is controlled via a pulse-width modulation generated by a control unit using a target duty cycle and a triangular-waveform voltage sequence. An actual duty cycle of a current pulse-width modulation is continuously ascertained from the switch signals and compared with the target duty cycle of the control unit.
-
公开(公告)号：US11962306B2
公开(公告)日：2024-04-16
申请号：US17361654
申请日：2021-06-29
申请人： NVIDIA Corporation
发明人： Kedar Rajpathak
IPC分类号： H03K5/19 , G01R13/02 , G01R29/02 , G01R29/027
CPC分类号： H03K5/19 , G01R13/0218 , G01R29/02 , G01R29/023 , G01R29/027 , G01R29/0273
摘要： Methods and apparatus are described for detecting anomalies in a clock signal. Example methods include sensing a clock signal that exhibits alternating phases during normal operation; responsive to sensing the start of a first phase, generating a pulse; and if the pulse terminates before sensing the end of the first phase, asserting a clock stopped detection signal. Example clock anomaly detection apparatus includes a clock signal input for coupling to a clock signal that, during normal operation, oscillates between first and second clock states. An anomaly detection output is asserted if the clock signal remains in the first clock state longer than a first phase expected duration or remains in the second clock state longer than a second phase expected duration.
-
公开(公告)号：US08736251B2
公开(公告)日：2014-05-27
申请号：US13616606
申请日：2012-09-14
申请人： Kelvin Yi-Tse Lai , Chen-Yi Lee
发明人： Kelvin Yi-Tse Lai , Chen-Yi Lee
CPC分类号： G01R23/15 , G01D5/243 , G01P15/125 , G01P21/00 , G01R23/10 , G01R25/08 , G01R29/023 , G01R29/027
摘要： A digital sensing apparatus includes a sensing unit capable of providing a sensing response associated with an environmental parameter, and a digital readout module including a reading unit for generating a pulse signal having a pulse width associated with the sensing response, and a converting unit. The converting unit includes a clock signal generator for generating a variable-frequency clock signal, and a counter operable to count a width value of the pulse width of the pulse signal using the clock signal, so as to generate a digital sensing code. The frequency of the clock signal from the clock signal generator is adjustable to adjust resolution of the width value of the pulse width of the pulse signal.
摘要翻译： 数字感测装置包括能够提供与环境参数相关联的感测响应的感测单元和包括用于产生具有与感测响应相关联的脉冲宽度的脉冲信号的读取单元的数字读出模块和转换单元。 转换单元包括用于产生可变频率时钟信号的时钟信号发生器和可用于使用时钟信号对脉冲信号的脉冲宽度的宽度值进行计数的计数器，以便产生数字感测代码。 来自时钟信号发生器的时钟信号的频率可调，以调节脉冲信号脉冲宽度宽度值的分辨率。
-
6.发明申请APPARATUS AND METHOD FOR DETERMINING VARIATION IN A PREDETERMINED PHYSICAL PROPERTY OF A CIRCUIT 有权用于确定电路预测物理性质的变化的装置和方法公开(公告)号：US20130120009A1
公开(公告)日：2013-05-16
申请号：US13297368
申请日：2011-11-16
IPC分类号： G01R31/02
CPC分类号： G01R29/023 , G01R19/0038 , G01R23/15 , G01R25/08 , G01R29/027 , G01R31/2881 , G01R31/30
摘要： Apparatus and method for determining variation in a predetermined physical property of a circuit. The apparatus includes monitored circuitry for generating output pulses, and configured such that each output pulse has a pulse width which is indicative of the current value of the predetermined physical property. Circuitry is then configured to receive both the output pulses generated by the monitored circuitry and an oscillating timing reference signal. With reference to the oscillating timing reference signal, the counter circuitry produces for each output pulse an associated count value indicative of the pulse width of that output pulse. Circuitry then compares the associated count values for at least two output pulses, in order to produce a comparison result used to determine the variation in the predetermined physical property. This provides a flexible mechanism for monitoring variations in a physical property on the fly during use of a data processing circuit.
摘要翻译： 用于确定电路的预定物理特性的变化的装置和方法。 该装置包括用于产生输出脉冲的监控电路，并且被配置为使得每个输出脉冲具有指示预定物理特性的当前值的脉冲宽度。 然后将电路配置为接收由被监视电路产生的输出脉冲和振荡定时参考信号。 参考振荡定时参考信号，计数器电路为每个输出脉冲产生指示该输出脉冲的脉冲宽度的相关联的计数值。 然后电路比较至少两个输出脉冲的相关联的计数值，以便产生用于确定预定物理特性的变化的比较结果。 这提供了一种用于在使用数据处理电路期间即时监测物理属性的变化的灵活机制。
-
公开(公告)号：US20120286807A1
公开(公告)日：2012-11-15
申请号：US13561534
申请日：2012-07-30
申请人： BERTRAM KÖLBLI
发明人： BERTRAM KÖLBLI
IPC分类号： G01R27/28
CPC分类号： G01R27/02 , G01R25/00 , G01R27/28 , G01R29/023 , G01V3/101 , G11C16/102 , H02H3/382
摘要： An electronic circuit is arranged in an external programming device and is used for contactless programming of a circuit to be programmed. The electronic circuit has a series resonant circuit that includes a transmitter coil and a capacitor. The transmitter coil of the series resonant circuit is used for inductive coupling to a receiver coil in the circuit to be programmed. For the purpose of evaluating the impedance that actually exists in the circuit to be programmed, there is provided a device for determining the value of the impedance from a phase difference between the control voltage of the series resonant circuit and the capacitor voltage of the series resonant circuit.
摘要翻译： 电子电路布置在外部编程装置中，并用于要编程的电路的非接触式编程。 电子电路具有包括发射线圈和电容器的串联谐振电路。 串联谐振电路的发射器线圈用于与要编程的电路中的接收器线圈的感应耦合。 为了评估实际存在于要编程的电路中的阻抗的目的，提供了一种用于根据串联谐振电路的控制电压和串联谐振电容器电压之间的相位差确定阻抗值的装置 电路。
-
公开(公告)号：US20080204046A1
公开(公告)日：2008-08-28
申请号：US12115672
申请日：2008-05-06
申请人： James E. Bartling
发明人： James E. Bartling
IPC分类号： G01R27/26
CPC分类号： G01R27/2605 , G01R29/023 , G01R31/2884 , G01R31/3167 , G01R31/31725 , G01R31/31727 , G04F10/04 , G04F10/105
摘要： A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times therebetween. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage.
摘要翻译： 在事件期间，通过从恒定电流源对已知值的电容器充电来确定事件的时间段。 电容器上的合成电压与事件时间周期成比例，可以根据合成电压和已知电容值计算。 在已知的时间段内通过从恒定电流源对电容器充电来测量电容。 电容器上的合成电压与其电容成比例，并且可以由所得到的电压和已知的时间周期来计算。 可以通过在事件开始时对第一电容器充电并且在事件结束时对第二电容器进行计数，同时计数它们之间的时钟时间来测量长时间段事件。 通过在事件开始和结束时在第一和第二电容器上充电电压，同时将其上的电压与参考电压进行事件的延迟。
-
公开(公告)号：US20060109032A1
公开(公告)日：2006-05-25
申请号：US11080555
申请日：2005-03-16
申请人： Toshikatsu Hosono
发明人： Toshikatsu Hosono
IPC分类号： H03D13/00
CPC分类号： G01R29/023 , G01R31/3016 , G01R31/31725
摘要： A timing verification apparatus calculates a pulse width variation coefficient based on a pulse width of an input clock signal, a delay value of the clock signal, and an operation frequency. The apparatus then calculates the pulse width for a delayed clock signal provided to a clock input terminal of a flip flop (FF) using the pulse width variation coefficient. Further, the apparatus compares the calculated pulse width with a standard value. The timing verification apparatus calculates the pulse width of the delayed clock signal provided to the clock input terminal of the FF using the pulse width of the clock signal, and a rise delay and a fall delay of the path. The apparatus considers on-chip variations and accurately executes timing verification for signals.
摘要翻译： 定时验证装置基于输入时钟信号的脉冲宽度，时钟信号的延迟值和操作频率来计算脉宽变化系数。 然后，该装置使用脉冲宽度变化系数来计算提供给触发器（FF）的时钟输入端的延迟时钟信号的脉冲宽度。 此外，该装置将所计算的脉冲宽度与标准值进行比较。 定时验证装置使用时钟信号的脉冲宽度和路径的上升延迟和下降延迟来计算提供给FF的时钟输入端的延迟时钟信号的脉冲宽度。 该装置考虑片上变化并准确地执行信号的定时验证。
-
10.发明授权公开(公告)号：US12039232B2
公开(公告)日：2024-07-16
申请号：US17134030
申请日：2020-12-24
发明人： Chun-An Lin , Wen-Che Shen , Chih-Wei Yeh , Po-Huan Chou , Chun-Chieh Chang , Yu-Hsun Wu
CPC分类号： G06F30/20 , G01R19/0084 , G01R29/023 , G06F30/30 , H03M1/66
摘要： A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.
-
-
-
-
-
-
-
-
-
搜索结果
67 条记录 (耗时 0.023 秒)
