公开(公告)号：US20180331690A1

公开(公告)日：2018-11-15

申请号：US15976708

申请日：2018-05-10

Applicant: UNIST (Ulsan National Institute of Science and Technology)

Inventor： Jae Joon KIM ,  Kyeong Hwan PARK

IPC: H03M1/46 ,  H03M7/16 ,  H03M1/36

CPC classification number: H03M1/462 ,  H03M1/145 ,  H03M1/361 ,  H03M1/365 ,  H03M1/466 ,  H03M1/68 ,  H03M7/165

Abstract: An SAR ADC combined with a flash ADC includes a clock generator, a DAC and a comparator. The SAR ADC combined with the flash ADC further includes an SAR logic unit using a successive approximation register control to determine, while a clock signal is a first state that is either high or low, a part of digital bits of the input signal based on a signal outputted from the comparator and control the DAC to generate a first analog signal based on the first determined digital bits and a flash ADC using a flash control to determine, during a second state switched from the first state, a remaining part of the digital bits of the input signal based on the first analog signal and control the DAC to generate a second analog signal based on the second determined digital bits in the second state.