公开(公告)号：US20180342602A1

公开(公告)日：2018-11-29

申请号：US15602114

申请日：2017-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： BIN TANG ,  Jubao Zhang ,  XIAOFEI HAN ,  CHAO JIANG ,  Hong Liao

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L27/11521

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.