公开(公告)号：US20180342602A1

公开(公告)日：2018-11-29

申请号：US15602114

申请日：2017-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： BIN TANG ,  Jubao Zhang ,  XIAOFEI HAN ,  CHAO JIANG ,  Hong Liao

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L27/11521

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.

公开(公告)号：US20170316830A1

公开(公告)日：2017-11-02

申请号：US15638352

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao Su ,  Chow Yee Lim ,  CHAO JIANG ,  Hong Liao

IPC: G11C16/04 ,  H01L27/11521 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L29/51 ,  H01L21/268

CPC classification number: H01L23/5226 ,  G11C16/0433 ,  H01L21/2686 ,  H01L21/28273 ,  H01L23/528 ,  H01L27/11521 ,  H01L29/518

Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.

公开(公告)号：US20170213854A1

公开(公告)日：2017-07-27

申请号：US15006123

申请日：2016-01-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： LANXIANG WANG ,  Hong Liao ,  CHAO JIANG

IPC: H01L27/12 ,  H01L21/77 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L21/77 ,  H01L27/1218 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L2021/775

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a gate layer on the substrate; forming a first gate dielectric layer on the gate layer; forming a first channel layer on the first region and a second channel layer on the second region; and forming a first source/drain on the first channel layer and a second source/drain on the second channel layer.