公开(公告)号：US20150303120A1

公开(公告)日：2015-10-22

申请号：US14256989

申请日：2014-04-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jubao Zhang ,  Xing Hua Zhang ,  Hong Liao

IPC: H01L21/66 ,  H01L23/522 ,  H01L21/78 ,  H01L23/00

Abstract: A method for fabricating semiconductor package structure is disclosed. The method includes: providing a wafer having a front side and a backside; forming a plurality of through-silicon vias (TSVs) in the wafer and a plurality of metal interconnections on the TSVs, in which the metal interconnections are exposed from the front side of the wafer; performing a monitoring step to screen for TSV failures from the backside of the wafer; and bonding the wafer to a substrate.

Abstract translation: 公开了半导体封装结构的制造方法。 该方法包括：提供具有正面和背面的晶片; 在晶片中形成多个通硅通孔（TSV）和在TSV上的多个金属互连，其中金属互连从晶片的前侧露出; 执行监视步骤以从晶片的背面屏蔽TSV故障; 并将晶片接合到基板。

公开(公告)号：US09780101B1

公开(公告)日：2017-10-03

申请号：US15361065

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Wenbo Ding ,  Xiaofei Han ,  Chien-Kee Pang ,  Yu-Yang Chen ,  Jubao Zhang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/788 ,  H01L27/11521 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.

公开(公告)号：US20150017798A1

公开(公告)日：2015-01-15

申请号：US13939182

申请日：2013-07-11

Applicant: United Microelectronics Corp.

Inventor： Jubao Zhang

IPC: H01L21/768

CPC classification number: H01L21/76898

Abstract: A method of manufacturing through-silicon-via (TSV) including the steps of sequentially forming a liner layer and a metal layer in a TSV hole, performing a chemical mechanical polishing process to remove the metal layer on the substrate so that the remaining metal layer in the TSV hole becomes a TSV, and forming a cap layer on the substrate without performing a NH3 treatment.

Abstract translation: 一种制造通硅通孔（TSV）的方法，包括以下步骤：在TSV孔中顺序地形成衬层和金属层，进行化学机械抛光工艺以除去衬底上的金属层，使剩余的金属层 在TSV孔中成为TSV，并且在不进行NH 3处理的基板上形成盖层。

公开(公告)号：US10147806B1

公开(公告)日：2018-12-04

申请号：US15602114

申请日：2017-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bin Tang ,  Jubao Zhang ,  Xiaofei Han ,  Chao Jiang ,  Hong Liao

IPC: H01L21/283 ,  H01L21/762 ,  H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11521 ,  H01L21/8234

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.

公开(公告)号：US20180342602A1

公开(公告)日：2018-11-29

申请号：US15602114

申请日：2017-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： BIN TANG ,  Jubao Zhang ,  XIAOFEI HAN ,  CHAO JIANG ,  Hong Liao

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/788 ,  H01L27/11521

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.

公开(公告)号：US20140147984A1

公开(公告)日：2014-05-29

申请号：US13685724

申请日：2012-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jubao Zhang

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a through silicon via structure includes the following steps. At first, a substrate is provided, and a dielectric layer is formed on the substrate. Subsequently, at least one first opening is formed in the dielectric layer, and the substrate exposed by the first opening is partially removed to form at least one via opening. A conductive material layer is then formed to fill the via opening and the first opening, and the conductive material layer is planarized.

Abstract translation: 通过硅通孔结构的制造方法包括以下步骤。 首先，设置基板，在基板上形成介电层。 随后，在电介质层中形成至少一个第一开口，并且部分去除由第一开口暴露的衬底以形成至少一个通孔。 然后形成导电材料层以填充通孔和第一开口，并且导电材料层被平坦化。