公开(公告)号：US20150115461A1

公开(公告)日：2015-04-30

申请号：US14066845

申请日：2013-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chou Yu ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/8221 ,  H01L23/544 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2223/54493 ,  H01L2224/9202 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2225/06596

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A first wafer is provided, which includes a first region, a second region, and a first semiconductor device disposed in the first region. No semiconductor device is disposed in the second region. A second wafer is provided, which includes a third region, a fourth region and a second semiconductor device disposed in the third region. No semiconductor device is disposed in the fourth region. The first region of the first wafer is overlapped with the fourth region of the second wafer. The second region of the first wafer is overlapped with the third region of the second wafer. A first conductive through via is formed to pass through the fourth region of the second wafer and the first region of the first wafer to electrically connect to the first semiconductor device.

Abstract translation: 提供半导体结构及其形成方法。 该方法包括以下步骤。 提供第一晶片，其包括第一区域，第二区域和设置在第一区域中的第一半导体器件。 在第二区域中不设置半导体器件。 提供第二晶片，其包括设置在第三区域中的第三区域，第四区域和第二半导体器件。 在第四区域中不设置半导体器件。 第一晶片的第一区域与第二晶片的第四区域重叠。 第一晶片的第二区域与第二晶片的第三区域重叠。 形成第一导电通孔以通过第二晶片的第四区域和第一晶片的第一区域以电连接到第一半导体器件。