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    METHOD FOR FORMING PROGRAMMABLE MEMORY
    1.
    发明申请
    METHOD FOR FORMING PROGRAMMABLE MEMORY 有权

    公开(公告)号：US20240397712A1

    公开(公告)日：2024-11-28

    申请号：US18792499

    申请日：2024-08-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

    IPC: H10B41/30 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788

    Abstract: An array of programmable memory includes a first floating gate and a second floating gate disposed on a substrate along a first direction, two spacers disposed between and parallel to the first floating gate and the second floating gate, a first word line sandwiched by one of the spacers and the adjacent first floating gate, and a second word line sandwiched by the other one of the spacers and the adjacent second floating gate, and two first spacers disposed on the substrate, wherein one of the first spacer is disposed between the first word line and the first floating gate, and another spacer is disposed between the second word line and the second floating gate, wherein each spacer has substantially the same shape as each first spacer.

    Semiconductor structure and manufacturing method thereof
    3.
    发明授权
    Semiconductor structure and manufacturing method thereof 有权
    半导体结构及其制造方法

    公开(公告)号：US09406771B1

    公开(公告)日：2016-08-02

    申请号：US14854161

    申请日：2015-09-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Yin Hsiao ,  Hsueh-Chun Hsiao ,  Tzu-Yun Chang ,  Ching-Chung Yang

    IPC: H01L29/78 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L21/28 ,  H01L21/265

    CPC classification number: H01L29/4983 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28105 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/4916 ,  H01L29/7833

    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate; a first and a second ion implantation regions of a first conductive type; a source and a drain diffusion regions formed in the first and the second ion implantation regions respectively; a channel diffusion region formed between the first and the second ion implantation regions; a gate layer disposed above the channel diffusion region and located between the source and the drain diffusion regions; and a third ion implantation region of a second conductive type formed in the gate layer, which extends in a first direction. The third ion implantation region is located above and covers two side portions of the channel diffusion region, the two side portions are adjacent to two edges, extending in a second direction perpendicular to the first direction, of the channel diffusion region.

    Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括基板; 第一导电类型的第一和第二离子注入区域; 在第一和第二离子注入区域中形成的源极和漏极扩散区域; 形成在第一和第二离子注入区之间的沟道扩散区; 栅极层，其设置在所述沟道扩散区域的上方且位于所述源极和漏极扩散区域之间; 以及形成在所述栅极层中的沿第一方向延伸的第二导电类型的第三离子注入区。 第三离子注入区域位于沟道扩散区域的上方并覆盖两个侧面部分，两个侧面部分与沟道扩散区域的垂直于第一方向的第二方向延伸的两个边缘相邻。

    METHOD FOR FORMING PROGRAMMABLE MEMORY
    10.
    发明申请
    METHOD FOR FORMING PROGRAMMABLE MEMORY 有权

    公开(公告)号：US20230033836A1

    公开(公告)日：2023-02-02

    申请号：US17960789

    申请日：2022-10-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsueh-Chun Hsiao ,  Yi-Ning Peng ,  Tzu-Yun Chang

    IPC: H01L27/11521 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/78

    Abstract: An array of electrically erasable programmable read only memory (EEPROM) includes a first row of floating gate, a second row of floating gate, two spacers, a first row of word line and a second row of word line. The first row of floating gate and the second row of floating gate are disposed on a substrate along a first direction. The two spacers are disposed between and parallel to the first row of floating gate and the second row of floating gate. The first row of word line is sandwiched by one of the spacers and the adjacent first row of floating gate, and the second row of word line is sandwiched by the other one of the spacers and the adjacent second row of floating gate. The present invention also provides a method of forming said array of electrically erasable programmable read only memory (EEPROM).

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