公开(公告)号：US12113028B2

公开(公告)日：2024-10-08

申请号：US17556149

申请日：2021-12-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Tse-Yao Huang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L23/5222 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/8313 ,  H01L2225/06593

Abstract: The present application discloses a semiconductor device with integrated decoupling alignment features. The semiconductor device includes a first wafer comprising a first substrate having a dielectric stack, a decoupling feature positioned in the dielectric stack under one of the plurality of first alignment marks, a plurality of first alignment marks positioned on the first substrate and parallel to each other; and a second wafer positioned on the first wafer and comprising a plurality of second alignment marks positioned above the plurality of first alignment marks. The plurality of second alignment marks are arranged parallel to the plurality of first alignment marks and adjacent to the plurality of first alignment marks in a top-view perspective. The plurality of first alignment marks and the plurality of second alignment marks comprise a fluorescence material. The decoupling feature has a bottle-shaped cross-sectional profile, and the decoupling feature comprises a porous low-k material.

公开(公告)号：US20240304602A1

公开(公告)日：2024-09-12

申请号：US18669679

申请日：2024-05-21

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Hiroshi MAEJIMA ,  Tetsuaki UTSUMI

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2225/06524 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

公开(公告)号：US20240038728A1

公开(公告)日：2024-02-01

申请号：US18356289

申请日：2023-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Wonil Lee

IPC: H01L25/065 ,  H10B80/00 ,  H01L23/31 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H10B80/00 ,  H01L23/3107 ,  H01L23/544 ,  H01L24/05 ,  H01L24/08 ,  H01L2225/06541 ,  H01L2225/06593 ,  H01L2223/54426 ,  H01L24/32 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/32221 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441

Abstract: A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip, and having widths narrower than a width of the first semiconductor chip, and a molded layer on an upper surface of the first semiconductor chip. The first semiconductor chip includes first front-surface pads, a first back-surface insulating layer divided into a first region and a second region, first back-surface pads in the first region, dummy pads in the second region, the dummy pads respectively having an upper surface on which a metal oxide film is disposed, and a first through-electrode electrically connecting the first front-surface pads and the first back-surface pads to each other. The plurality of second semiconductor chips respectively includes second front-surface pads, second back-surface pads, and a second through-electrode electrically connecting the second front-surface pads and the second back-surface pads to each other.

公开(公告)号：US11855065B2

公开(公告)日：2023-12-26

申请号：US17409439

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Hong Wan Ng ,  Seng Kim Ye

IPC: H01L25/00 ,  H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/33 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06135 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/1033 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/143 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15174 ,  H01L2924/15182 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05599

Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.

公开(公告)号：US20230395438A1

公开(公告)日：2023-12-07

申请号：US17831810

申请日：2022-06-03

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Nagesh Vodrahalli ,  Chih Yang Li ,  Xuyi Yang ,  Cong Zhang

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L22/20 ,  H01L25/0652 ,  H01L24/48 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06593 ,  H01L2224/48225 ,  H01L2924/1438 ,  H01L2924/37001 ,  H01L2924/1011 ,  H01L2924/182 ,  H01L2924/1431 ,  H01L2224/48148 ,  H01L2225/06562

Abstract: A semiconductor device includes a die stack having dies selected into the stack based on their thicknesses. After the dies are formed on a wafer and thinned, a metrology tool is used to determine the thicknesses of the dies in the wafer. These thicknesses are stored in a known thickness die (KTD) map, along with other information such as their standard and average deviations and their classification into a binning class. In one example, dies which have been classified into bin 1 (having an optimal thickness) are selected to provide a high capacity highly reliable semiconductor device. In a further example, dies of different bins are mixed and matched to provide a uniform, highly controlled overall die stack height.

公开(公告)号：US20230361086A1

公开(公告)日：2023-11-09

申请号：US18357137

申请日：2023-07-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L25/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/08 ,  H01L24/32 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/33 ,  H01L25/18 ,  H01L25/50 ,  H01L24/89 ,  H01L21/78 ,  H01L24/97 ,  H01L21/568 ,  H01L24/83 ,  H01L21/6835 ,  H01L24/85 ,  H01L23/49816 ,  H01L24/73 ,  H01L24/92 ,  H01L21/561 ,  H01L24/05 ,  H01L2224/83005 ,  H01L2225/06593 ,  H01L2224/80895 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2224/80006 ,  H01L2224/80896 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/32225 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/08147 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/85005 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/95001

Abstract: A package structure includes a plurality of stacked die units and an insulating encapsulant. The plurality of stacked die units is stacked on top of one another, where each of the plurality of stacked die units include a first semiconductor die, a first bonding chip. The first semiconductor die has a plurality of first bonding pads. The first bonding chip is stacked on the first semiconductor die and has a plurality of first bonding structure. The plurality of first bonding structures is bonded to the plurality of first bonding pads through hybrid bonding. The insulating encapsulant is encapsulating the plurality of stacked die units.

公开(公告)号：US20230307423A1

公开(公告)日：2023-09-28

申请号：US18328389

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min KIM ,  Dae Won HA

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L23/481 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80894 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06593 ,  H01L2224/08145

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

公开(公告)号：US11756844B2

公开(公告)日：2023-09-12

申请号：US17170120

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Mark E. Tuttle

IPC: H01L23/532 ,  H01L23/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/04 ,  H01L25/00

CPC classification number: H01L23/10 ,  H01L23/04 ,  H01L24/17 ,  H01L24/67 ,  H01L24/70 ,  H01L24/73 ,  H01L24/81 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/50 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17517 ,  H01L2224/8109 ,  H01L2224/81075 ,  H01L2224/8182 ,  H01L2224/81122 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/01029 ,  H01L2924/3025 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate; a die attached over the substrate; and a metal enclosure continuously encircling a space and extending vertically between the substrate and the die.

公开(公告)号：US11749614B2

公开(公告)日：2023-09-05

申请号：US17340445

申请日：2021-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongyeop Kim ,  Seil Oh ,  Eunji Kim ,  Kwangwuk Park ,  Jihak Yu

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/544 ,  H01L23/481 ,  H01L25/0657 ,  H01L2223/54426 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06593

Abstract: A through-silicon via (TSV) key for overlay measurement includes: a first TSV extending through at least a portion of a substrate in a first direction that is perpendicular to a top surface of the substrate; and at least one ring pattern, which is apart from and surrounds the first TSV in a second direction that is parallel to the top surface of the substrate, the at least one ring pattern being arranged in a layer that is lower than a top surface of the first TSV in the first direction, wherein an inner measurement point corresponds to the first TSV, an outer measurement point corresponds to the at least one ring pattern, and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV.

公开(公告)号：US20180286836A1

公开(公告)日：2018-10-04

申请号：US15921563

申请日：2018-03-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Justin Hiroki Sato ,  Bomy Chen ,  Walter Lundy

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0217 ,  H01L2224/0219 ,  H01L2224/04042 ,  H01L2224/05091 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/16502 ,  H01L2224/48091 ,  H01L2224/81143 ,  H01L2224/81805 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/07025 ,  H01L2224/45099

Abstract: A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.