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公开(公告)号：US09961450B2
公开(公告)日：2018-05-01
申请号：US15246561
申请日：2016-08-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Sheng Hsu , Weng-Yi Chen , En-Chan Chen , Shih-Wei Li , Guo-Chih Wei
CPC classification number: H04R17/025 , B81B3/0021 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C2201/013 , H04R1/06 , H04R7/04 , H04R7/20 , H04R17/02 , H04R19/005 , H04R31/003 , H04R31/006 , H04R2201/003
Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.
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公开(公告)号：US20180027337A1
公开(公告)日：2018-01-25
申请号：US15246561
申请日：2016-08-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Sheng Hsu , Weng-Yi Chen , En-Chan Chen , Shih-Wei Li , Guo-Chih Wei
CPC classification number: H04R17/025 , B81B3/0021 , B81B2201/0257 , B81B2203/0127 , B81B2203/0315 , B81C1/00158 , B81C2201/013 , H04R1/06 , H04R7/04 , H04R7/20 , H04R17/02 , H04R19/005 , H04R31/003 , H04R31/006 , H04R2201/003
Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.
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