公开(公告)号：US10446689B1

公开(公告)日：2019-10-15

申请号：US16274190

申请日：2019-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chien-Ming Lai ,  Yen-Chen Chen ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Seng Wah Liau ,  Han Chuan Fang

IPC: H01L29/768 ,  H01L29/417 ,  H01L29/66 ,  H01L21/4757 ,  H01L29/786

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

公开(公告)号：US10446688B1

公开(公告)日：2019-10-15

申请号：US16190090

申请日：2018-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jen-Po Huang ,  Chien-Ming Lai ,  Yen-Chen Chen ,  Sheng-Yao Huang ,  Hui-Ling Chen ,  Seng Wah Liau ,  Han Chuan Fang

IPC: H01L29/786 ,  H01L29/417 ,  H01L21/4757 ,  H01L29/66

Abstract: An oxide semiconductor device includes a substrate, a first patterned oxide semiconductor layer, a source electrode, a drain electrode, and a sidewall spacer. The first patterned oxide semiconductor layer is disposed on the substrate. The source electrode and the drain electrode are disposed on the first patterned oxide semiconductor layer. The sidewall spacer is disposed on a sidewall of the first patterned oxide semiconductor layer. The sidewall spacer may be used to improve the performance of blocking impurities from entering the first patterned oxide semiconductor layer via the sidewall, and the electrical performance and the reliability of the oxide semiconductor device may be enhanced accordingly.

公开(公告)号：US09117695B1

公开(公告)日：2015-08-25

申请号：US14328697

申请日：2014-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ji Gang Pan ,  Han Chuan Fang ,  Boon-Tiong Neo

IPC: H01L21/8238 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10894 ,  H01L21/28273 ,  H01L21/3212 ,  H01L21/76801 ,  H01L27/11531 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a memory region and a periphery region; forming a memory cell on the memory region; forming a first polysilicon layer on the periphery region and the memory cell; forming a patterned cap layer on the periphery region; forming a second polysilicon layer on the first polysilicon layer and the patterned cap layer; and performing a chemical mechanical polishing (CMP) process to remove the second polysilicon layer, wherein the chemical mechanical polishing process comprises an abrasive of greater than 13% and a remove rate of less than 30 Angstroms/second.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有存储区域和周边区域的衬底; 在所述存储器区域上形成存储器单元; 在周边区域和存储单元上形成第一多晶硅层; 在周边区域上形成图案化的盖层; 在所述第一多晶硅层和所述图案化盖层上形成第二多晶硅层; 以及进行化学机械抛光（CMP）工艺以去除所述第二多晶硅层，其中所述化学机械抛光工艺包括大于13％的磨料和小于30埃/秒的去除率。