公开(公告)号：US09754788B2

公开(公告)日：2017-09-05

申请号：US14797478

申请日：2015-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ji-Gang Pan ,  Han-Chuan Fang ,  Boon-Tiong Neo

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/321 ,  H01L27/11531 ,  H01L27/11541

CPC classification number: H01L21/28273 ,  H01L21/32056 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L27/11531 ,  H01L27/11541

Abstract: A manufacturing method of a semiconductor structure having an array area and a periphery area is provided. The manufacturing method includes the following steps. A substrate is provided. A plurality of trenches is formed on the substrate. The plurality of trenches is filled with insulating material to form at least one first insulating layer. A polysilicon layer is deposited on the substrate and the first insulating layer. A photoresist mask is formed on the periphery area. A portion of the polysilicon layer on the array area is etched, such that a top surface of the polysilicon layer on the array area is higher than the first insulating layer and lower than a top surface of the polysilicon layer on the periphery area. The photoresist mask is removed. A planarization process is implemented to remove a portion of the polysilicon layer on the array area and on the periphery area.

公开(公告)号：US09117695B1

公开(公告)日：2015-08-25

申请号：US14328697

申请日：2014-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ji Gang Pan ,  Han Chuan Fang ,  Boon-Tiong Neo

IPC: H01L21/8238 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10894 ,  H01L21/28273 ,  H01L21/3212 ,  H01L21/76801 ,  H01L27/11531 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a memory region and a periphery region; forming a memory cell on the memory region; forming a first polysilicon layer on the periphery region and the memory cell; forming a patterned cap layer on the periphery region; forming a second polysilicon layer on the first polysilicon layer and the patterned cap layer; and performing a chemical mechanical polishing (CMP) process to remove the second polysilicon layer, wherein the chemical mechanical polishing process comprises an abrasive of greater than 13% and a remove rate of less than 30 Angstroms/second.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有存储区域和周边区域的衬底; 在所述存储器区域上形成存储器单元; 在周边区域和存储单元上形成第一多晶硅层; 在周边区域上形成图案化的盖层; 在所述第一多晶硅层和所述图案化盖层上形成第二多晶硅层; 以及进行化学机械抛光（CMP）工艺以去除所述第二多晶硅层，其中所述化学机械抛光工艺包括大于13％的磨料和小于30埃/秒的去除率。

公开(公告)号：US20170018432A1

公开(公告)日：2017-01-19

申请号：US14797478

申请日：2015-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ji-Gang Pan ,  Han-Chuan Fang ,  Boon-Tiong Neo

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/3205

CPC classification number: H01L21/28273 ,  H01L21/32056 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/32139 ,  H01L27/11531 ,  H01L27/11541

Abstract: A manufacturing method of a semiconductor structure having an array area and a periphery area is provided. The manufacturing method includes the following steps. A substrate is provided. A plurality of trenches is formed on the substrate. The plurality of trenches is filled with insulating material to form at least one first insulating layer. A polysilicon layer is deposited on the substrate and the first insulating layer. A photoresist mask is formed on the periphery area. A portion of the polysilicon layer on the array area is etched, such that a top surface of the polysilicon layer on the array area is higher than the first insulating layer and lower than a top surface of the polysilicon layer on the periphery area. The photoresist mask is removed. A planarization process is implemented to remove a portion of the polysilicon layer on the array area and on the periphery area.

Abstract translation: 提供具有阵列区域和周边区域的半导体结构体的制造方法。 该制造方法包括以下步骤。 提供基板。 在基板上形成多个沟槽。 多个沟槽用绝缘材料填充以形成至少一个第一绝缘层。 多晶硅层沉积在衬底和第一绝缘层上。 在周边区域上形成光刻胶掩模。 蚀刻阵列区域上的多晶硅层的一部分，使得阵列区域上的多晶硅层的顶表面高于第一绝缘层并且低于外围区域上的多晶硅层的顶表面。 去除光致抗蚀剂掩模。 实现平坦化处理以去除阵列区域和外围区域上的多晶硅层的一部分。

公开(公告)号：US08901003B1

公开(公告)日：2014-12-02

申请号：US14021419

申请日：2013-09-09

Applicant: United Microelectronics Corp.

Inventor： Ji-Gang Pan ,  Han-Chuan Fang ,  Boon-Tiong Neo

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/321 ,  H01L21/02

CPC classification number: H01L21/30625 ,  H01L27/1464 ,  H01L27/14683

Abstract: A polishing method of a semiconductor device is disclosed. A substrate having a first side and a second side opposite to the first side is provided. The substrate has a device layer formed on the first side and a plurality of trench isolation structures therein extending from the first side to the second side. A main polishing step is performed to the second side of the substrate until a surface of at least one of the trench isolation structures is exposed. An auxiliary polishing step is then performed to the second side of the substrate. Besides, a silicon-to-oxide selectivity of the main polishing step is different from a silicon-to-oxide selectivity of the auxiliary step.

Abstract translation: 公开了一种半导体器件的抛光方法。 提供具有与第一侧相对的第一侧和第二侧的基板。 衬底具有形成在第一侧上的器件层和其中从第一侧延伸到第二侧的多个沟槽隔离结构。 对衬底的第二侧进行主抛光步骤，直到暴露出至少一个沟槽隔离结构的表面。 然后对衬底的第二侧进行辅助抛光步骤。 此外，主抛光步骤的硅 - 氧化物选择性不同于辅助步骤的硅 - 氧化物选择性。