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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200235101A1

    公开(公告)日：2020-07-23

    申请号：US16841702

    申请日：2020-04-07

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Cheng Tsai ,  Chih-Chi Cheng ,  Chia-Wei Wu ,  Ger-Pin Lin

    IPC: H01L27/108

    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

    Method for forming a layout pattern
    4.
    发明授权
    Method for forming a layout pattern 审中-公开

    公开(公告)号：US10670958B2

    公开(公告)日：2020-06-02

    申请号：US15937825

    申请日：2018-03-27

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Ying-Chiao Wang ,  Yu-Cheng Tung ,  Li-Wei Feng ,  Chien-Ting Ho

    IPC: G03F1/36 ,  G03F7/20 ,  H01L27/108

    Abstract: A method of forming a layout pattern is disclosed. First, an array comprising a plurality of main features is provided wherein the main features are arranged into a plurality of rows along a first direction and are parallel and staggered along a second direction. Assistant features are inserted into each row of the main features. A shortest distance d1 between the main features in row n to the main features in row n+1 and a shortest distance d2 between the main feature in row n−1 to the main feature in row n+1 are obtained. The assistance features inserted in row n of the main features are then adjusted according to the difference between the distances d1 and d2. After that, the main features and the assistant features are output to a photo mask.

    INSULATING STRUCTURE AND METHOD OF FORMING THE SAME
    5.
    发明申请
    INSULATING STRUCTURE AND METHOD OF FORMING THE SAME 审中-公开

    公开(公告)号：US20200035685A1

    公开(公告)日：2020-01-30

    申请号：US16590387

    申请日：2019-10-02

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Li-Wei Feng

    IPC: H01L27/108 ,  H01L21/311

    Abstract: A method of forming insulating structures in a semiconductor device is provided in the present invention, which includes the steps of forming a first mask layer with mandrels and a peripheral portion surrounding the mandrels, forming spacers on sidewalls of first mask layer, filling up the space between spacers with a second mask layer, removing the spacers to form opening patterns, performing an etch process with the first mask layer and the second mask layer as an etch mask to form trenches in the substrate, and filling up the trenches with an insulating material to form insulating structures.

    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
    7.
    发明申请
    SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190296019A1

    公开(公告)日：2019-09-26

    申请号：US15961827

    申请日：2018-04-24

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Po-Han Wu ,  Li-Wei Feng ,  Shih-Han Hung ,  Fu-Che Lee ,  Chien-Cheng Tsai

    IPC: H01L27/108 ,  H01L21/768

    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20190206874A1

    公开(公告)日：2019-07-04

    申请号：US16294934

    申请日：2019-03-07

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

    IPC: H01L27/108

    CPC classification number: H01L27/10885 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

    Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.

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